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Searched refs:read_sysreg_el1 (Results 1 – 12 of 12) sorted by relevance

/arch/arm64/kvm/hyp/vhe/
A Dsysreg-sr.c24 __vcpu_assign_sys_reg(vcpu, ESR_EL2, read_sysreg_el1(SYS_ESR)); in __sysreg_save_vel2_state()
25 __vcpu_assign_sys_reg(vcpu, AFSR0_EL2, read_sysreg_el1(SYS_AFSR0)); in __sysreg_save_vel2_state()
26 __vcpu_assign_sys_reg(vcpu, AFSR1_EL2, read_sysreg_el1(SYS_AFSR1)); in __sysreg_save_vel2_state()
27 __vcpu_assign_sys_reg(vcpu, FAR_EL2, read_sysreg_el1(SYS_FAR)); in __sysreg_save_vel2_state()
28 __vcpu_assign_sys_reg(vcpu, MAIR_EL2, read_sysreg_el1(SYS_MAIR)); in __sysreg_save_vel2_state()
29 __vcpu_assign_sys_reg(vcpu, VBAR_EL2, read_sysreg_el1(SYS_VBAR)); in __sysreg_save_vel2_state()
31 __vcpu_assign_sys_reg(vcpu, AMAIR_EL2, read_sysreg_el1(SYS_AMAIR)); in __sysreg_save_vel2_state()
52 __vcpu_assign_sys_reg(vcpu, TCR_EL2, read_sysreg_el1(SYS_TCR)); in __sysreg_save_vel2_state()
59 __vcpu_assign_sys_reg(vcpu, PIR_EL2, read_sysreg_el1(SYS_PIR)); in __sysreg_save_vel2_state()
71 val = read_sysreg_el1(SYS_CNTKCTL); in __sysreg_save_vel2_state()
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A Dtlb.c43 val = cxt->tcr = read_sysreg_el1(SYS_TCR); in enter_vmid_context()
46 val = cxt->sctlr = read_sysreg_el1(SYS_SCTLR); in enter_vmid_context()
A Dswitch.c346 spsr = read_sysreg_el1(SYS_SPSR); in kvm_hyp_handle_eret()
369 elr = read_sysreg_el1(SYS_ELR); in kvm_hyp_handle_eret()
/arch/arm64/kvm/hyp/include/hyp/
A Dsysreg-sr.h140 ctxt_sys_reg(ctxt, TCR_EL1) = read_sysreg_el1(SYS_TCR); in __sysreg_save_el1_state()
142 ctxt_sys_reg(ctxt, TCR2_EL1) = read_sysreg_el1(SYS_TCR2); in __sysreg_save_el1_state()
145 ctxt_sys_reg(ctxt, PIR_EL1) = read_sysreg_el1(SYS_PIR); in __sysreg_save_el1_state()
150 ctxt_sys_reg(ctxt, POR_EL1) = read_sysreg_el1(SYS_POR); in __sysreg_save_el1_state()
152 ctxt_sys_reg(ctxt, ESR_EL1) = read_sysreg_el1(SYS_ESR); in __sysreg_save_el1_state()
155 ctxt_sys_reg(ctxt, FAR_EL1) = read_sysreg_el1(SYS_FAR); in __sysreg_save_el1_state()
156 ctxt_sys_reg(ctxt, MAIR_EL1) = read_sysreg_el1(SYS_MAIR); in __sysreg_save_el1_state()
157 ctxt_sys_reg(ctxt, VBAR_EL1) = read_sysreg_el1(SYS_VBAR); in __sysreg_save_el1_state()
165 ctxt_sys_reg(ctxt, TFSR_EL1) = read_sysreg_el1(SYS_TFSR); in __sysreg_save_el1_state()
170 ctxt_sys_reg(ctxt, ELR_EL1) = read_sysreg_el1(SYS_ELR); in __sysreg_save_el1_state()
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A Dswitch.h579 sve_state->zcr_el1 = read_sysreg_el1(SYS_ZCR); in __hyp_sve_save_host()
623 zcr_el1 = read_sysreg_el1(SYS_ZCR); in fpsimd_lazy_switch_to_host()
/arch/arm64/kvm/hyp/nvhe/
A Ddebug-sr.c34 *pmscr_el1 = read_sysreg_el1(SYS_PMSCR); in __debug_save_spe()
56 *saved_trfcr = read_sysreg_el1(SYS_TRFCR); in __trace_do_switch()
100 if (!(read_sysreg_el1(SYS_BRBCR) & (BRBCR_ELx_E0BRE | BRBCR_ELx_ExBRE))) in __debug_save_brbe()
108 *brbcr_el1 = read_sysreg_el1(SYS_BRBCR); in __debug_save_brbe()
A Dtlb.c86 val = cxt->tcr = read_sysreg_el1(SYS_TCR); in enter_vmid_context()
92 val = cxt->sctlr = read_sysreg_el1(SYS_SCTLR); in enter_vmid_context()
A Dswitch.c88 val = read_sysreg_el1(SYS_TCR); in __deactivate_traps()
91 val = read_sysreg_el1(SYS_SCTLR); in __deactivate_traps()
A Dhyp-main.c29 __vcpu_assign_sys_reg(vcpu, ZCR_EL1, read_sysreg_el1(SYS_ZCR)); in __hyp_sve_save_guest()
/arch/arm64/include/asm/
A Dkvm_hyp.h29 #define read_sysreg_el1(r) read_sysreg_s(r##_EL12) macro
63 #define read_sysreg_el1(r) read_sysreg_elx(r, _EL1, _EL12) macro
/arch/arm64/kvm/
A Dat.c471 config->ttbr0 = read_sysreg_el1(SYS_TTBR0); in __mmu_config_save()
472 config->ttbr1 = read_sysreg_el1(SYS_TTBR1); in __mmu_config_save()
473 config->tcr = read_sysreg_el1(SYS_TCR); in __mmu_config_save()
474 config->mair = read_sysreg_el1(SYS_MAIR); in __mmu_config_save()
476 config->tcr2 = read_sysreg_el1(SYS_TCR2); in __mmu_config_save()
478 config->pir = read_sysreg_el1(SYS_PIR); in __mmu_config_save()
479 config->pire0 = read_sysreg_el1(SYS_PIRE0); in __mmu_config_save()
482 config->por_el1 = read_sysreg_el1(SYS_POR); in __mmu_config_save()
486 config->sctlr = read_sysreg_el1(SYS_SCTLR); in __mmu_config_save()
A Dsys_regs.c172 val = read_sysreg_el1(SYS_CNTKCTL); in vcpu_read_sys_reg()

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