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Searched refs:readl (Results 1 – 25 of 130) sorted by relevance

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/arch/arm/mach-dove/
A Dmpp.c60 readl(DOVE_MPP_CTRL4_VIRT_BASE)); in dove_mpp_dump_regs()
63 readl(DOVE_PMU_MPP_GENERAL_CTRL)); in dove_mpp_dump_regs()
65 pr_debug("MPP_GENERAL: %08x\n", readl(DOVE_MPP_GENERAL_VIRT_BASE)); in dove_mpp_dump_regs()
70 u32 mpp_gen_cfg = readl(DOVE_MPP_GENERAL_VIRT_BASE); in dove_mpp_cfg_nfc()
81 u32 mpp_ctrl4 = readl(DOVE_MPP_CTRL4_VIRT_BASE); in dove_mpp_cfg_au1()
82 u32 ssp_ctrl1 = readl(DOVE_SSP_CTRL_STATUS_1); in dove_mpp_cfg_au1()
83 u32 mpp_gen_ctrl = readl(DOVE_MPP_GENERAL_VIRT_BASE); in dove_mpp_cfg_au1()
84 u32 global_cfg_2 = readl(DOVE_GLOBAL_CONFIG_2); in dove_mpp_cfg_au1()
121 u32 mpp_ctrl4 = readl(DOVE_MPP_CTRL4_VIRT_BASE); in dove_mpp_conf_grp()
/arch/arm/mach-clps711x/
A Dboard-dt.c48 id[0] = readl(CLPS711X_VIRT_BASE + UNIQID); in clps711x_init()
49 id[1] = readl(CLPS711X_VIRT_BASE + RANDID0); in clps711x_init()
50 id[2] = readl(CLPS711X_VIRT_BASE + RANDID1); in clps711x_init()
51 id[3] = readl(CLPS711X_VIRT_BASE + RANDID2); in clps711x_init()
52 id[4] = readl(CLPS711X_VIRT_BASE + RANDID3); in clps711x_init()
53 system_rev = SYSFLG1_VERID(readl(CLPS711X_VIRT_BASE + SYSFLG1)); in clps711x_init()
/arch/arm/plat-orion/
A Dtime.c67 return ~readl(timer_base + TIMER0_VAL_OFF); in orion_read_sched_clock()
89 u = readl(bridge_base + BRIDGE_MASK_OFF); in orion_clkevt_next_event()
101 u = readl(timer_base + TIMER_CTRL_OFF); in orion_clkevt_next_event()
118 u = readl(timer_base + TIMER_CTRL_OFF); in orion_clkevt_shutdown()
122 u = readl(bridge_base + BRIDGE_MASK_OFF); in orion_clkevt_shutdown()
145 u = readl(bridge_base + BRIDGE_MASK_OFF); in orion_clkevt_set_periodic()
149 u = readl(timer_base + TIMER_CTRL_OFF); in orion_clkevt_set_periodic()
188 return ~readl(timer_base + TIMER0_VAL_OFF); in orion_delay_timer_read()
223 u = readl(bridge_base + BRIDGE_MASK_OFF); in orion_time_init()
225 u = readl(timer_base + TIMER_CTRL_OFF); in orion_time_init()
A Dpcie.c57 return readl(base + PCIE_DEV_ID_OFF) >> 16; in orion_pcie_dev_id()
62 return readl(base + PCIE_DEV_REV_OFF) & 0xff; in orion_pcie_rev()
72 return !(readl(base + PCIE_CTRL_OFF) & PCIE_CTRL_X1_MODE); in orion_pcie_x4_mode()
77 u32 stat = readl(base + PCIE_STAT_OFF); in orion_pcie_get_local_bus_nr()
86 stat = readl(base + PCIE_STAT_OFF); in orion_pcie_set_local_bus_nr()
103 reg = readl(base + PCIE_DEBUG_CTRL); in orion_pcie_reset()
203 mask = readl(base + PCIE_MASK_OFF); in orion_pcie_setup()
217 *val = readl(base + PCIE_CONF_DATA_OFF); in orion_pcie_rd_conf()
236 *val = readl(base + PCIE_CONF_DATA_OFF); in orion_pcie_rd_conf_tlp()
240 *val = readl(base + PCIE_HEADER_LOG_4_OFF); in orion_pcie_rd_conf_tlp()
[all …]
A Dgpio.c101 u = readl(GPIO_IO_CONF(ochip)); in __set_direction()
113 u = readl(GPIO_OUT(ochip)); in __set_level()
126 u = readl(GPIO_BLINK_EN(ochip)); in __set_blinking()
188 val = readl(GPIO_DATA_IN(ochip)) ^ readl(GPIO_IN_POL(ochip)); in orion_gpio_get()
190 val = readl(GPIO_OUT(ochip)); in orion_gpio_get()
382 u = readl(GPIO_IN_POL(ochip)); in gpio_irq_set_type()
386 u = readl(GPIO_IN_POL(ochip)); in gpio_irq_set_type()
392 v = readl(GPIO_IN_POL(ochip)) ^ readl(GPIO_DATA_IN(ochip)); in gpio_irq_set_type()
397 u = readl(GPIO_IN_POL(ochip)); in gpio_irq_set_type()
416 cause = readl(GPIO_DATA_IN(ochip)) & readl(GPIO_LEVEL_MASK(ochip)); in gpio_irq_handler()
[all …]
/arch/arm/mach-s3c/
A Dsetup-usb-phy-s3c64xx.c28 writel(readl(S3C64XX_OTHERS) | S3C64XX_OTHERS_USBMASK, S3C64XX_OTHERS); in s3c_usb_otgphy_init()
31 phyclk = readl(S3C_PHYCLK) & ~S3C_PHYCLK_CLKSEL_MASK; in s3c_usb_otgphy_init()
54 writel((readl(S3C_PHYPWR) & ~S3C_PHYPWR_NORMAL_MASK), S3C_PHYPWR); in s3c_usb_otgphy_init()
68 writel((readl(S3C_PHYPWR) | S3C_PHYPWR_ANALOG_POWERDOWN | in s3c_usb_otgphy_exit()
71 writel(readl(S3C64XX_OTHERS) & ~S3C64XX_OTHERS_USBMASK, S3C64XX_OTHERS); in s3c_usb_otgphy_exit()
/arch/arm/mach-sunxi/
A Dmc_smp.c171 reg = readl(prcm_base + PRCM_CPU_PO_RST_CTRL(cluster)); in sunxi_cpu_powerup()
177 reg = readl(r_cpucfg_base + in sunxi_cpu_powerup()
193 reg = readl(cpucfg_base + CPUCFG_CX_RST_CTRL(cluster)); in sunxi_cpu_powerup()
227 reg = readl(prcm_base + PRCM_CPU_PO_RST_CTRL(cluster)); in sunxi_cpu_powerup()
232 reg = readl(r_cpucfg_base + in sunxi_cpu_powerup()
241 reg = readl(cpucfg_base + CPUCFG_CX_RST_CTRL(cluster)); in sunxi_cpu_powerup()
275 reg = readl(prcm_base + PRCM_CPU_PO_RST_CTRL(cluster)); in sunxi_cluster_powerup()
281 reg = readl(r_cpucfg_base + in sunxi_cluster_powerup()
290 reg = readl(cpucfg_base + CPUCFG_CX_RST_CTRL(cluster)); in sunxi_cluster_powerup()
327 reg = readl(cpucfg_base + CPUCFG_CX_RST_CTRL(cluster)); in sunxi_cluster_powerup()
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A Dplatsmp.c90 reg = readl(cpucfg_membase + CPUCFG_GEN_CTRL_REG); in sun6i_smp_boot_secondary()
94 reg = readl(cpucfg_membase + CPUCFG_DBG_CTL1_REG); in sun6i_smp_boot_secondary()
103 reg = readl(prcm_membase + PRCM_CPU_PWROFF_REG); in sun6i_smp_boot_secondary()
111 reg = readl(cpucfg_membase + CPUCFG_DBG_CTL1_REG); in sun6i_smp_boot_secondary()
174 reg = readl(cpucfg_membase + CPUCFG_GEN_CTRL_REG); in sun8i_smp_boot_secondary()
178 reg = readl(prcm_membase + PRCM_CPU_PWROFF_REG); in sun8i_smp_boot_secondary()
/arch/arm/mach-ux500/
A Dpm.c47 u32 val = readl(PRCM_A9_MASK_REQ); in prcmu_gic_decouple()
54 readl(PRCM_A9_MASK_REQ); in prcmu_gic_decouple()
65 u32 val = readl(PRCM_A9_MASK_REQ); in prcmu_gic_recouple()
115 it = readl(PRCM_ARMITVAL31TO0 + i * 4); in prcmu_pending_irq()
116 im = readl(PRCM_ARMITMSK31TO0 + i * 4); in prcmu_pending_irq()
132 return readl(PRCM_ARM_WFI_STANDBY) & in prcmu_is_cpu_in_wfi()
/arch/arm/mach-mvebu/
A Dpmsu.c212 reg = readl(pmsu_mp_base + L2C_NFABRIC_PM_CTL); in mvebu_v7_pmsu_enable_l2_powerdown_onidle()
237 reg = readl(pmsu_mp_base + PMSU_STATUS_AND_MASK(hw_cpu)); in mvebu_v7_pmsu_idle_prepare()
246 reg = readl(pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu)); in mvebu_v7_pmsu_idle_prepare()
347 reg = readl(pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu)); in mvebu_v7_pmsu_idle_exit()
352 reg = readl(pmsu_mp_base + PMSU_STATUS_AND_MASK(hw_cpu)); in mvebu_v7_pmsu_idle_exit()
450 reg = readl(mpsoc_base + MPCORE_RESET_CTL); in armada_38x_cpuidle_init()
457 reg = readl(pmsu_mp_base + PMSU_POWERDOWN_DELAY); in armada_38x_cpuidle_init()
544 reg = readl(pmsu_mp_base + PMSU_STATUS_AND_MASK(cpu)); in mvebu_pmsu_dfs_request_local()
551 reg = readl(pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(cpu)); in mvebu_pmsu_dfs_request_local()
562 reg = readl(pmsu_mp_base + PMSU_STATUS_AND_MASK(cpu)); in mvebu_pmsu_dfs_request_local()
[all …]
/arch/sparc/kernel/
A Debus.c62 val = readl(p->regs + EBDMA_CSR); in __ebus_dma_reset()
77 csr = readl(p->regs + EBDMA_CSR); in ebus_dma_irq()
136 csr = readl(p->regs + EBDMA_CSR); in ebus_dma_irq_enable()
142 csr = readl(p->regs + EBDMA_CSR); in ebus_dma_irq_enable()
163 csr = readl(p->regs + EBDMA_CSR); in ebus_dma_unregister()
186 csr = readl(p->regs + EBDMA_CSR); in ebus_dma_request()
231 return readl(p->regs + EBDMA_COUNT); in ebus_dma_residue()
237 return readl(p->regs + EBDMA_ADDR); in ebus_dma_addr()
247 orig_csr = csr = readl(p->regs + EBDMA_CSR); in ebus_dma_enable()
/arch/x86/kernel/
A Dvsmp_64.c35 cap = readl(address); in set_vsmp_ctl()
36 ctl = readl(address + 4); in set_vsmp_ctl()
53 ctl = readl(address + 4); in set_vsmp_ctl()
116 topology = readl(address); in vsmp_cap_cpus()
/arch/arm/mach-mv78xx0/
A Dcommon.c52 switch ((readl(SAMPLE_AT_RESET_LOW) >> 5) & 7) { in get_hclk()
70 readl(SAMPLE_AT_RESET_LOW)); in get_hclk()
85 cfg = (readl(SAMPLE_AT_RESET_LOW) >> 8) & 0x3f; in get_pclk_l2clk()
87 cfg = (readl(SAMPLE_AT_RESET_LOW) >> 14) & 0x3f; in get_pclk_l2clk()
110 switch ((readl(SAMPLE_AT_RESET_HIGH) >> 6) & 7) { in get_tclk()
119 readl(SAMPLE_AT_RESET_HIGH)); in get_tclk()
402 return !!(readl(CPU_CONTROL) & L2_WRITETHROUGH); in is_l2_writethrough()
/arch/m68k/include/asm/
A Dio_no.h73 #define readl readl macro
74 static inline u32 readl(const volatile void __iomem *addr) in readl() function
103 #define readl __raw_readl macro
/arch/mips/loongson2ef/common/
A Dpm.c78 writel(readl(LOONGSON_CHIPCFG) & ~0x7, LOONGSON_CHIPCFG); in wait_for_wakeup_events()
101 cached_cpu_freq = readl(LOONGSON_CHIPCFG); in loongson_suspend_enter()
104 writel(readl(LOONGSON_CHIPCFG) & ~0x7, LOONGSON_CHIPCFG); in loongson_suspend_enter()
/arch/m68k/coldfire/
A Dm53xx.c372 if (!(readl(MCF_SDRAMC_SDCR) & MCF_SDRAMC_SDCR_REF)) { in sdramc_init()
429 writel(readl(MCF_SDRAMC_SDCR) | MCF_SDRAMC_SDCR_IPALL, MCF_SDRAMC_SDCR); in sdramc_init()
434 writel(readl(MCF_SDRAMC_SDCR) | MCF_SDRAMC_SDCR_IREF, MCF_SDRAMC_SDCR); in sdramc_init()
435 writel(readl(MCF_SDRAMC_SDCR) | MCF_SDRAMC_SDCR_IREF, MCF_SDRAMC_SDCR); in sdramc_init()
448 writel(readl(MCF_SDRAMC_SDCR) & ~MCF_SDRAMC_SDCR_MODE_EN, in sdramc_init()
505 if (readl(MCF_SDRAMC_SDCR) & MCF_SDRAMC_SDCR_REF) in clock_pll()
507 writel(readl(MCF_SDRAMC_SDCR) & ~MCF_SDRAMC_SDCR_CKE, in clock_pll()
530 if (readl(MCF_SDRAMC_SDCR) & MCF_SDRAMC_SDCR_REF) in clock_pll()
532 writel(readl(MCF_SDRAMC_SDCR) | MCF_SDRAMC_SDCR_CKE, in clock_pll()
A Dm5249.c97 r = readl(MCFINTC2_INTPRI_REG(MCF_IRQ_I2C1)); in m5249_i2c_init()
113 gpio = readl(MCFSIM2_GPIOINTENABLE); in m5249_smc91x_init()
116 gpio = readl(MCFINTC2_INTPRI5); in m5249_smc91x_init()
A Dintc-5249.c23 imr = readl(MCFSIM2_GPIOINTENABLE); in intc2_irq_gpio_mask()
31 imr = readl(MCFSIM2_GPIOINTENABLE); in intc2_irq_gpio_unmask()
/arch/arm/mach-omap1/
A Dtime.c77 return readl(&timer->read_tim); in omap_mpu_timer_read()
84 writel(readl(&timer->cntl) | MPU_TIMER_AR, &timer->cntl); in omap_mpu_set_autoreset()
91 writel(readl(&timer->cntl) & ~MPU_TIMER_AR, &timer->cntl); in omap_mpu_remove_autoreset()
114 writel(readl(&timer->cntl) & ~MPU_TIMER_ST, &timer->cntl); in omap_mpu_timer_stop()
/arch/arm/include/asm/
A Dcputype.h159 return readl(BASEADDR_V7M_SCB + offset); in read_cpuid_ext()
203 return readl(BASEADDR_V7M_SCB + V7M_SCB_CPUID); in read_cpuid_id()
208 return readl(BASEADDR_V7M_SCB + V7M_SCB_CTR); in read_cpuid_cachetype()
213 return readl(BASEADDR_V7M_SCB + MPU_TYPE); in read_cpuid_mputype()
/arch/mips/pic32/pic32mzda/
A Dconfig.c30 v = readl(pic32_conf_base + offset); in pic32_conf_get_reg_field()
43 v = readl(pic32_conf_base + offset); in pic32_conf_modify_atomic()
111 pic32_reset_status = readl(pic32_conf_base + PIC32_RCON); in pic32_config_init()
/arch/arm/mach-orion5x/
A Dboard-mss2.c73 reg = readl(RSTOUTn_MASK); in mss2_power_off()
77 reg = readl(CPU_SOFT_RESET); in mss2_power_off()
/arch/arm/mach-versatile/
A Dintegrator.c39 return readl(cm_base + INTEGRATOR_HDR_CTRL_OFFSET); in cm_get()
53 val = readl(cm_base + INTEGRATOR_HDR_CTRL_OFFSET) & ~mask; in cm_control()
/arch/arm/mach-pxa/
A Dgumstix.c138 if (!(readl(OSCC) & OSCC_OOK)) in gumstix_setup_bt_clock()
143 writel(readl(OSCC) | OSCC_OON, OSCC); in gumstix_setup_bt_clock()
145 if (readl(OSCC) & OSCC_OOK) in gumstix_setup_bt_clock()
/arch/arm/mach-socfpga/
A Docram.c67 u32 value = readl(ioaddr); in ecc_set_bits()
75 u32 value = readl(ioaddr); in ecc_clear_bits()
83 u32 value = readl(ioaddr); in ecc_test_bits()

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