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/arch/parisc/include/asm/
A Dasmregs.h11 rp: .reg %r2
16 dp: .reg %r27
19 sl: .reg %r29
20 sp: .reg %r30
28 gp: .reg r27
29 ap: .reg r29
33 r0: .reg %r0
34 r1: .reg %r1
35 r2: .reg %r2
36 r3: .reg %r3
[all …]
/arch/mips/include/asm/
A Dasm-eva.h38 #define kernel_sd(reg, addr) user_sw(reg, addr) argument
106 #define kernel_ll(reg, addr) ll reg, addr argument
107 #define kernel_sc(reg, addr) sc reg, addr argument
108 #define kernel_lw(reg, addr) lw reg, addr argument
111 #define kernel_lh(reg, addr) lh reg, addr argument
112 #define kernel_lb(reg, addr) lb reg, addr argument
114 #define kernel_sw(reg, addr) sw reg, addr argument
117 #define kernel_sh(reg, addr) sh reg, addr argument
118 #define kernel_sb(reg, addr) sb reg, addr argument
128 #define kernel_sd(reg, addr) sd reg, addr argument
[all …]
/arch/mips/include/asm/octeon/
A Dcvmx-fau.h188 reg ^= SWIZZLE_32; in cvmx_fau_fetch_and_add32()
203 reg ^= SWIZZLE_16; in cvmx_fau_fetch_and_add16()
216 reg ^= SWIZZLE_8; in cvmx_fau_fetch_and_add8()
263 reg ^= SWIZZLE_32; in cvmx_fau_tagwait_fetch_and_add32()
287 reg ^= SWIZZLE_16; in cvmx_fau_tagwait_fetch_and_add16()
310 reg ^= SWIZZLE_8; in cvmx_fau_tagwait_fetch_and_add8()
540 reg ^= SWIZZLE_32; in cvmx_fau_atomic_add32()
553 reg ^= SWIZZLE_16; in cvmx_fau_atomic_add16()
565 reg ^= SWIZZLE_8; in cvmx_fau_atomic_add8()
590 reg ^= SWIZZLE_32; in cvmx_fau_atomic_write32()
[all …]
/arch/arm64/tools/
A Dgen-sysreg.awk119 reg = $2
140 reg = null
154 reg = $2
195 reg = null
231 parse_bitdef(reg, "RES0", $2)
241 parse_bitdef(reg, "RES1", $2)
262 parse_bitdef(reg, field, $2)
272 parse_bitdef(reg, field, $2)
282 parse_bitdef(reg, field, $2)
295 parse_bitdef(reg, field, $2)
[all …]
/arch/arm/boot/dts/aspeed/
A Dibm-power9-dual.dtsi6 reg = <0 0>;
23 reg = <0>;
27 reg = <1>;
31 reg = <2>;
35 reg = <3>;
39 reg = <4>;
43 reg = <5>;
47 reg = <6>;
51 reg = <7>;
208 reg = <1>;
[all …]
A Dibm-power11-quad.dtsi132 reg = <0 0>;
403 reg = <0>;
419 reg = <0>;
435 reg = <0>;
451 reg = <0>;
485 reg = <1 0>;
756 reg = <0>;
772 reg = <0>;
788 reg = <0>;
837 reg = <2 0>;
[all …]
A Daspeed-bmc-facebook-fuji.dts221 reg = <2>;
246 reg = <0>;
260 reg = <1>;
266 reg = <2>;
272 reg = <3>;
278 reg = <4>;
284 reg = <5>;
290 reg = <6>;
296 reg = <7>;
316 reg = <0>;
[all …]
A Daspeed-bmc-facebook-cmm.dts342 reg = <0>;
447 reg = <1>;
552 reg = <2>;
657 reg = <3>;
762 reg = <4>;
867 reg = <5>;
972 reg = <6>;
1077 reg = <7>;
1196 reg = <0>;
1202 reg = <1>;
[all …]
A Daspeed-bmc-facebook-yosemite4.dts72 reg = <0>;
182 reg = <0x21>;
189 reg = <0x22>;
201 reg = <0x23>;
208 reg = <0x24>;
590 reg = <0>;
617 reg = <1>;
644 reg = <2>;
671 reg = <3>;
712 reg = <0>;
[all …]
A Daspeed-bmc-ibm-everest.dts458 reg = <0>;
494 reg = <1>;
530 reg = <2>;
603 reg = <0>;
639 reg = <1>;
675 reg = <2>;
711 reg = <3>;
4025 reg = <5>;
4029 reg = <6>;
4033 reg = <7>;
[all …]
A Dibm-power10-quad.dtsi9 reg = <0x20>;
14 reg = <0 0>;
37 reg = <0x20>;
42 reg = <0 0>;
65 reg = <0x20>;
70 reg = <0 0>;
93 reg = <0x20>;
98 reg = <0 0>;
121 reg = <0x20>;
1204 reg = <3>;
[all …]
A Daspeed-bmc-ibm-fuji.dts456 reg = <0>;
492 reg = <1>;
528 reg = <2>;
599 reg = <0>;
635 reg = <1>;
671 reg = <2>;
707 reg = <3>;
755 reg = <0>;
791 reg = <1>;
827 reg = <2>;
[all …]
/arch/x86/include/asm/
A Dxor_avx.h38 #define BLOCK(i, reg) \ in xor_avx_2() argument
41 asm volatile("vxorps %0, %%ymm" #reg ", %%ymm" #reg : : \ in xor_avx_2()
69 asm volatile("vxorps %0, %%ymm" #reg ", %%ymm" #reg : : \ in xor_avx_3()
71 asm volatile("vxorps %0, %%ymm" #reg ", %%ymm" #reg : : \ in xor_avx_3()
101 asm volatile("vxorps %0, %%ymm" #reg ", %%ymm" #reg : : \ in xor_avx_4()
103 asm volatile("vxorps %0, %%ymm" #reg ", %%ymm" #reg : : \ in xor_avx_4()
105 asm volatile("vxorps %0, %%ymm" #reg ", %%ymm" #reg : : \ in xor_avx_4()
137 asm volatile("vxorps %0, %%ymm" #reg ", %%ymm" #reg : : \ in xor_avx_5()
139 asm volatile("vxorps %0, %%ymm" #reg ", %%ymm" #reg : : \ in xor_avx_5()
141 asm volatile("vxorps %0, %%ymm" #reg ", %%ymm" #reg : : \ in xor_avx_5()
[all …]
/arch/m68k/math-emu/
A Dmulti_arith.h29 reg->lowmant = reg->mant.m32[1] << (8 - cnt); in fp_denormalize()
30 reg->mant.m32[1] = (reg->mant.m32[1] >> cnt) | in fp_denormalize()
32 reg->mant.m32[0] = reg->mant.m32[0] >> cnt; in fp_denormalize()
35 reg->lowmant = reg->mant.m32[1] >> (cnt - 8); in fp_denormalize()
38 reg->mant.m32[1] = (reg->mant.m32[1] >> cnt) | in fp_denormalize()
40 reg->mant.m32[0] = reg->mant.m32[0] >> cnt; in fp_denormalize()
51 reg->lowmant = reg->mant.m32[0] >> (cnt - 40); in fp_denormalize()
58 reg->lowmant = reg->mant.m32[0] || reg->mant.m32[1]; in fp_denormalize()
71 reg->mant.m32[0] = (reg->mant.m32[0] << shift) | (reg->mant.m32[1] >> (32 - shift)); in fp_overnormalize()
108 reg->lowmant = (reg->mant.m32[1] << 7) | (reg->lowmant ? 1 : 0); in fp_addcarry()
[all …]
/arch/sh/include/mach-common/mach/
A Dmagicpanelr2.h19 #define SETBITS_OUTB(mask, reg) __raw_writeb(__raw_readb(reg) | mask, reg) argument
20 #define SETBITS_OUTW(mask, reg) __raw_writew(__raw_readw(reg) | mask, reg) argument
21 #define SETBITS_OUTL(mask, reg) __raw_writel(__raw_readl(reg) | mask, reg) argument
22 #define CLRBITS_OUTB(mask, reg) __raw_writeb(__raw_readb(reg) & ~mask, reg) argument
23 #define CLRBITS_OUTW(mask, reg) __raw_writew(__raw_readw(reg) & ~mask, reg) argument
24 #define CLRBITS_OUTL(mask, reg) __raw_writel(__raw_readl(reg) & ~mask, reg) argument
/arch/arm64/kvm/hyp/include/hyp/
A Ddebug-sr.h21 #define save_debug(ptr,reg,nr) \ argument
23 case 15: ptr[15] = read_debug(reg, 15); \
25 case 14: ptr[14] = read_debug(reg, 14); \
35 case 9: ptr[9] = read_debug(reg, 9); \
37 case 8: ptr[8] = read_debug(reg, 8); \
39 case 7: ptr[7] = read_debug(reg, 7); \
41 case 6: ptr[6] = read_debug(reg, 6); \
43 case 5: ptr[5] = read_debug(reg, 5); \
45 case 4: ptr[4] = read_debug(reg, 4); \
47 case 3: ptr[3] = read_debug(reg, 3); \
[all …]
/arch/arm/mach-sunxi/
A Dmc_smp.c118 u32 reg; in sunxi_cpu_power_switch_set() local
123 if (reg == 0x00) { in sunxi_cpu_power_switch_set()
160 u32 reg; in sunxi_cpu_powerup() local
180 writel(reg, r_cpucfg_base + in sunxi_cpu_powerup()
235 writel(reg, r_cpucfg_base + in sunxi_cpu_powerup()
255 u32 reg; in sunxi_cluster_powerup() local
284 writel(reg, r_cpucfg_base + in sunxi_cluster_powerup()
431 u32 reg; in sunxi_cluster_cache_disable() local
482 u32 reg; in sunxi_cpu_powerdown() local
506 u32 reg; in sunxi_cluster_powerdown() local
[all …]
/arch/arm/mach-omap2/
A Dsdrc.h24 #define OMAP_SDRC_REGADDR(reg) (omap2_sdrc_base + (reg)) argument
25 #define OMAP_SMS_REGADDR(reg) (omap2_sms_base + (reg)) argument
34 static inline u32 sdrc_read_reg(u16 reg) in sdrc_read_reg() argument
43 writel_relaxed(val, OMAP_SMS_REGADDR(reg)); in sms_write_reg()
46 static inline u32 sms_read_reg(u16 reg) in sms_read_reg() argument
100 #define OMAP242X_SDRC_REGADDR(reg) \ argument
102 #define OMAP243X_SDRC_REGADDR(reg) \ argument
104 #define OMAP34XX_SDRC_REGADDR(reg) \ argument
191 #define OMAP242X_SMS_REGADDR(reg) \ argument
193 #define OMAP243X_SMS_REGADDR(reg) \ argument
[all …]
/arch/arm64/boot/dts/nvidia/
A Dtegra186-p2771-0000.dts27 reg = <0>;
35 reg = <1>;
53 reg = <0>;
61 reg = <1>;
79 reg = <0>;
87 reg = <1>;
105 reg = <0>;
113 reg = <1>;
131 reg = <0>;
139 reg = <1>;
[all …]
A Dtegra194-p3509-0000.dtsi23 reg = <0>;
31 reg = <1>;
49 reg = <0>;
57 reg = <1>;
75 reg = <0>;
84 reg = <1>;
102 reg = <0>;
110 reg = <1>;
127 reg = <0>;
135 reg = <1>;
[all …]
A Dtegra210-p2371-2180.dts42 reg = <0>;
55 reg = <0x2c>;
82 reg = <0x57>;
138 reg = <0>;
146 reg = <1>;
164 reg = <0>;
172 reg = <1>;
190 reg = <0>;
198 reg = <1>;
216 reg = <0>;
[all …]
A Dtegra194-p2972-0000.dts28 reg = <0>;
36 reg = <1>;
54 reg = <0>;
62 reg = <1>;
80 reg = <0>;
88 reg = <1>;
106 reg = <0>;
114 reg = <1>;
132 reg = <0>;
140 reg = <1>;
[all …]
/arch/arm/mach-omap1/
A Dmux.h27 #define MUX_REG(reg, mode_offset, mode) .mux_reg_name = "FUNC_MUX_CTRL_"#reg, \ argument
28 .mux_reg = FUNC_MUX_CTRL_##reg, \
32 #define PULL_REG(reg, bit, status) .pull_name = "PULL_DWN_CTRL_"#reg, \ argument
37 #define PU_PD_REG(reg, status) .pu_pd_name = "PU_PD_SEL_"#reg, \ argument
38 .pu_pd_reg = PU_PD_SEL_##reg, \
41 #define MUX_REG_7XX(reg, mode_offset, mode) .mux_reg_name = "OMAP7XX_IO_CONF_"#reg, \ argument
46 #define PULL_REG_7XX(reg, bit, status) .pull_name = "OMAP7XX_IO_CONF_"#reg, \ argument
53 #define MUX_REG(reg, mode_offset, mode) .mux_reg = FUNC_MUX_CTRL_##reg, \ argument
57 #define PULL_REG(reg, bit, status) .pull_reg = PULL_DWN_CTRL_##reg, \ argument
61 #define PU_PD_REG(reg, status) .pu_pd_reg = PU_PD_SEL_##reg, \ argument
[all …]
/arch/arm64/boot/dts/microchip/
A Dsparx5_pcb135_board.dtsi203 reg = <0>;
206 reg = <1>;
209 reg = <2>;
212 reg = <3>;
215 reg = <4>;
218 reg = <5>;
221 reg = <6>;
224 reg = <7>;
227 reg = <8>;
230 reg = <9>;
[all …]
/arch/mips/pci/
A Dops-sni.c26 if ((devfn > 255) || (reg > 255)) in set_config_address()
35 (reg & 0xfc); in set_config_address()
50 *val = inb(PCIMT_CONFIG_DATA + (reg & 3)); in pcimt_read()
53 *val = inw(PCIMT_CONFIG_DATA + (reg & 2)); in pcimt_read()
73 outb(val, PCIMT_CONFIG_DATA + (reg & 3)); in pcimt_write()
76 outw(val, PCIMT_CONFIG_DATA + (reg & 2)); in pcimt_write()
93 if ((devfn > 255) || (reg > 255) || (busno > 255)) in pcit_set_config_address()
125 *val = inb(PCIMT_CONFIG_DATA + (reg & 3)); in pcit_read()
128 *val = inw(PCIMT_CONFIG_DATA + (reg & 2)); in pcit_read()
147 outb(val, PCIMT_CONFIG_DATA + (reg & 3)); in pcit_write()
[all …]

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