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Searched refs:reg_base (Results 1 – 16 of 16) sorted by relevance

/arch/sh/drivers/pci/
A Dpci-sh7780.c100 addr = __raw_readl(hose->reg_base + SH4_PCIALR); in sh7780_pci_err_irq()
140 __raw_writel(cmd, hose->reg_base + SH4_PCIINT); in sh7780_pci_err_irq()
169 __raw_writel(0, hose->reg_base + SH4_PCIAINT); in sh7780_pci_setup_irqs()
229 tmp = __raw_readl(hose->reg_base + SH4_PCICR); in sh7780_pci66_init()
231 __raw_writel(tmp, hose->reg_base + SH4_PCICR); in sh7780_pci66_init()
255 chan->reg_base = 0xfe040000; in sh7780_pci_init()
262 chan->reg_base + SH4_PCICR); in sh7780_pci_init()
297 chan->reg_base + SH4_PCICR); in sh7780_pci_init()
309 chan->reg_base + SH4_PCILSR1); in sh7780_pci_init()
325 chan->reg_base + SH4_PCILSR0); in sh7780_pci_init()
[all …]
A Dpci-sh4.h173 __raw_writel(val, chan->reg_base + reg); in pci_write_reg()
179 return __raw_readl(chan->reg_base + reg); in pci_read_reg()
A Dpcie-sh7786.h568 __raw_writel(val, chan->reg_base + reg); in pci_write_reg()
574 return __raw_readl(chan->reg_base + reg); in pci_read_reg()
A Dpci-sh7751.c83 chan->reg_base = 0xfe200000; in sh7751_pci_init()
A Dpcie-sh7786.c121 .reg_base = start, \
240 clk->enable_reg = (void __iomem *)(chan->reg_base + SH4A_PCIEPHYCTLR); in pcie_clk_init()
/arch/arm/mach-rockchip/
A Drockchip.c25 void __iomem *reg_base; in rockchip_timer_init() local
32 reg_base = ioremap(RK3288_TIMER6_7_PHYS, SZ_16K); in rockchip_timer_init()
33 if (reg_base) { in rockchip_timer_init()
34 writel(0, reg_base + 0x30); in rockchip_timer_init()
35 writel(0xffffffff, reg_base + 0x20); in rockchip_timer_init()
36 writel(0xffffffff, reg_base + 0x24); in rockchip_timer_init()
37 writel(1, reg_base + 0x30); in rockchip_timer_init()
39 iounmap(reg_base); in rockchip_timer_init()
/arch/powerpc/boot/
A Dns16550.c31 static unsigned char *reg_base; variable
36 out_8(reg_base + (UART_FCR << reg_shift), 0x06); in ns16550_open()
42 while ((in_8(reg_base + (UART_LSR << reg_shift)) & UART_LSR_THRE) == 0); in ns16550_putc()
43 out_8(reg_base, c); in ns16550_putc()
48 while ((in_8(reg_base + (UART_LSR << reg_shift)) & UART_LSR_DR) == 0); in ns16550_getc()
49 return in_8(reg_base); in ns16550_getc()
54 return ((in_8(reg_base + (UART_LSR << reg_shift)) & UART_LSR_DR) != 0); in ns16550_tstc()
62 if (dt_get_virtual_reg(devp, (void **)&reg_base, 1) < 1) { in ns16550_console_init()
69 reg_base += be32_to_cpu(reg_offset); in ns16550_console_init()
/arch/sparc/kernel/
A Dsbus.c224 imap += reg_base; in sbus_build_irq()
239 iclr = reg_base + SYSIO_ICLR_SLOT0; in sbus_build_irq()
242 iclr = reg_base + SYSIO_ICLR_SLOT1; in sbus_build_irq()
245 iclr = reg_base + SYSIO_ICLR_SLOT2; in sbus_build_irq()
249 iclr = reg_base + SYSIO_ICLR_SLOT3; in sbus_build_irq()
281 afsr_reg = reg_base + SYSIO_UE_AFSR; in sysio_ue_handler()
282 afar_reg = reg_base + SYSIO_UE_AFAR; in sysio_ue_handler()
355 afsr_reg = reg_base + SYSIO_CE_AFSR; in sysio_ce_handler()
356 afar_reg = reg_base + SYSIO_CE_AFAR; in sysio_ce_handler()
533 reg_base + ECC_CONTROL); in sysio_register_error_handlers()
[all …]
A Dprom_irqtrans.c653 unsigned long reg_base = (unsigned long) _data; in sbus_of_build_irq() local
674 imap += reg_base; in sbus_of_build_irq()
687 iclr = reg_base + SYSIO_ICLR_SLOT0; in sbus_of_build_irq()
690 iclr = reg_base + SYSIO_ICLR_SLOT1; in sbus_of_build_irq()
693 iclr = reg_base + SYSIO_ICLR_SLOT2; in sbus_of_build_irq()
697 iclr = reg_base + SYSIO_ICLR_SLOT3; in sbus_of_build_irq()
/arch/powerpc/platforms/powernv/
A Dopal-xscom.c94 u64 reg, reg_base, reg_cnt, val; in scom_debug_read() local
99 reg_base = off >> 3; in scom_debug_read()
103 rc = opal_scom_read(ent->chip, reg_base, reg, &val); in scom_debug_read()
125 u64 reg, reg_base, reg_cnt, val; in scom_debug_write() local
130 reg_base = off >> 3; in scom_debug_write()
136 rc = opal_scom_write(ent->chip, reg_base, reg, val); in scom_debug_write()
/arch/x86/platform/intel-quark/
A Dimr.c43 int reg_base; member
112 u32 reg = imr_id * IMR_NUM_REGS + idev->reg_base; in imr_read()
144 u32 reg = imr_id * IMR_NUM_REGS + idev->reg_base; in imr_write()
589 idev->reg_base = QUARK_X1000_IMR_REGBASE; in imr_init()
/arch/sh/include/asm/
A Dpci.h27 unsigned long reg_base; member
/arch/powerpc/kvm/
A Dmpic.c197 gpa_t reg_base; member
1389 ret = kvm_mpic_read_internal(opp, addr - opp->reg_base, &u.val); in kvm_mpic_read()
1430 ret = kvm_mpic_write_internal(opp, addr - opp->reg_base, in kvm_mpic_write()
1450 opp->reg_base, OPENPIC_REG_SIZE, in map_mmio()
1472 if (base == opp->reg_base) in set_base_addr()
1478 opp->reg_base = base; in set_base_addr()
1568 attr64 = opp->reg_base; in mpic_get_attr()
/arch/arm64/boot/dts/nvidia/
A Dtegra132.dtsi867 reg = <0x0 0x700e2000 0x0 0x600>, /* 0: SOC_THERM reg_base */
868 <0x0 0x70040000 0x0 0x200>; /* 2: CCROC reg_base */
A Dtegra210.dtsi1339 reg = <0x0 0x700e2000 0x0 0x600>, /* SOC_THERM reg_base */
1340 <0x0 0x60006000 0x0 0x400>; /* CAR reg_base */
/arch/arm/boot/dts/nvidia/
A Dtegra124.dtsi949 reg = <0x0 0x700e2000 0x0 0x600>, /* SOC_THERM reg_base */
950 <0x0 0x60006000 0x0 0x400>; /* CAR reg_base */

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