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Searched refs:reg_val (Results 1 – 16 of 16) sorted by relevance

/arch/powerpc/platforms/powernv/
A Dopal-fadump.h83 __be64 reg_val; member
88 u64 reg_val) in opal_fadump_set_regval_regnum() argument
92 regs->gpr[reg_num] = reg_val; in opal_fadump_set_regval_regnum()
98 regs->ctr = reg_val; in opal_fadump_set_regval_regnum()
101 regs->link = reg_val; in opal_fadump_set_regval_regnum()
104 regs->xer = reg_val; in opal_fadump_set_regval_regnum()
107 regs->dar = reg_val; in opal_fadump_set_regval_regnum()
110 regs->dsisr = reg_val; in opal_fadump_set_regval_regnum()
113 regs->nip = reg_val; in opal_fadump_set_regval_regnum()
116 regs->msr = reg_val; in opal_fadump_set_regval_regnum()
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/arch/mips/pci/
A Dfixup-malta.c70 unsigned char reg_val; in malta_piix_func0_fixup() local
85 if (reg_val & PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_DISABLE) in malta_piix_func0_fixup()
88 pci_irq[PCIA+i] = piixirqmap[reg_val & in malta_piix_func0_fixup()
98 pci_read_config_byte(pdev, PIIX4_FUNC0_TOM, &reg_val); in malta_piix_func0_fixup()
99 pci_write_config_byte(pdev, PIIX4_FUNC0_TOM, reg_val | in malta_piix_func0_fixup()
109 pci_read_config_byte(pdev, PIIX4_FUNC0_SERIRQC, &reg_val); in malta_piix_func0_fixup()
124 unsigned char reg_val; in malta_piix_func1_fixup() local
132 &reg_val); in malta_piix_func1_fixup()
134 reg_val|PIIX4_FUNC1_IDETIM_PRIMARY_HI_IDE_DECODE_EN); in malta_piix_func1_fixup()
136 &reg_val); in malta_piix_func1_fixup()
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/arch/arm/mach-qcom/
A Dplatsmp.c84 u32 reg_val; in cortex_a7_release_secondary() local
111 reg_val &= ~CORE_MEM_CLAMP; in cortex_a7_release_secondary()
113 reg_val |= L2DT_SLP; in cortex_a7_release_secondary()
117 reg_val = (reg_val | BIT(17)) & ~CLAMP; in cortex_a7_release_secondary()
124 reg_val |= CORE_PWRD_UP; in cortex_a7_release_secondary()
219 unsigned reg_val; in kpssv2_release_secondary() local
264 reg_val |= 0x3f << BHS_SEG_SHIFT; in kpssv2_release_secondary()
279 reg_val = COREPOR_RST | CLAMP; in kpssv2_release_secondary()
284 reg_val &= ~CLAMP; in kpssv2_release_secondary()
289 reg_val &= ~COREPOR_RST; in kpssv2_release_secondary()
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/arch/riscv/kvm/
A Dvcpu_onereg.c270 unsigned long reg_val; in kvm_riscv_vcpu_get_reg_config() local
424 unsigned long reg_val; in kvm_riscv_vcpu_get_reg_core() local
432 reg_val = cntx->sepc; in kvm_riscv_vcpu_get_reg_core()
457 unsigned long reg_val; in kvm_riscv_vcpu_set_reg_core() local
468 cntx->sepc = reg_val; in kvm_riscv_vcpu_set_reg_core()
624 reg_val); in kvm_riscv_vcpu_set_reg_csr()
647 *reg_val = 0; in riscv_vcpu_get_isa_ext_single()
673 if (reg_val == 1 && in riscv_vcpu_set_isa_ext_single()
676 else if (!reg_val && in riscv_vcpu_set_isa_ext_single()
749 reg_val = 0; in kvm_riscv_vcpu_get_reg_isa_ext()
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A Dvcpu_fp.c87 void *reg_val; in kvm_riscv_vcpu_get_reg_fp() local
94 reg_val = &cntx->fp.f.fcsr; in kvm_riscv_vcpu_get_reg_fp()
97 reg_val = &cntx->fp.f.f[reg_num]; in kvm_riscv_vcpu_get_reg_fp()
105 reg_val = &cntx->fp.d.fcsr; in kvm_riscv_vcpu_get_reg_fp()
110 reg_val = &cntx->fp.d.f[reg_num]; in kvm_riscv_vcpu_get_reg_fp()
116 if (copy_to_user(uaddr, reg_val, KVM_REG_SIZE(reg->id))) in kvm_riscv_vcpu_get_reg_fp()
132 void *reg_val; in kvm_riscv_vcpu_set_reg_fp() local
139 reg_val = &cntx->fp.f.fcsr; in kvm_riscv_vcpu_set_reg_fp()
142 reg_val = &cntx->fp.f.f[reg_num]; in kvm_riscv_vcpu_set_reg_fp()
150 reg_val = &cntx->fp.d.fcsr; in kvm_riscv_vcpu_set_reg_fp()
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A Dvcpu_sbi.c208 unsigned long reg_val) in riscv_vcpu_set_sbi_ext_single() argument
213 if (reg_val != 1 && reg_val != 0) in riscv_vcpu_set_sbi_ext_single()
229 unsigned long *reg_val) in riscv_vcpu_get_sbi_ext_single() argument
246 unsigned long reg_val, bool enable) in riscv_vcpu_set_sbi_ext_multi() argument
266 unsigned long *reg_val) in riscv_vcpu_get_sbi_ext_multi() argument
295 unsigned long reg_val, reg_subtype; in kvm_riscv_vcpu_set_reg_sbi_ext() local
332 unsigned long reg_val, reg_subtype; in kvm_riscv_vcpu_get_reg_sbi_ext() local
340 reg_val = 0; in kvm_riscv_vcpu_get_reg_sbi_ext()
349 reg_val = ~reg_val; in kvm_riscv_vcpu_get_reg_sbi_ext()
371 unsigned long reg_subtype, reg_val; in kvm_riscv_vcpu_set_reg_sbi() local
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A Dvcpu_sbi_sta.c164 unsigned long *reg_val) in kvm_riscv_vcpu_get_reg_sbi_sta() argument
168 *reg_val = (unsigned long)vcpu->arch.sta.shmem; in kvm_riscv_vcpu_get_reg_sbi_sta()
172 *reg_val = upper_32_bits(vcpu->arch.sta.shmem); in kvm_riscv_vcpu_get_reg_sbi_sta()
174 *reg_val = 0; in kvm_riscv_vcpu_get_reg_sbi_sta()
185 unsigned long reg_val) in kvm_riscv_vcpu_set_reg_sbi_sta() argument
192 vcpu->arch.sta.shmem = reg_val; in kvm_riscv_vcpu_set_reg_sbi_sta()
195 vcpu->arch.sta.shmem = reg_val; in kvm_riscv_vcpu_set_reg_sbi_sta()
202 vcpu->arch.sta.shmem = ((gpa_t)reg_val << 32); in kvm_riscv_vcpu_set_reg_sbi_sta()
204 } else if (reg_val != 0) { in kvm_riscv_vcpu_set_reg_sbi_sta()
A Dvcpu_timer.c168 u64 reg_val; in kvm_riscv_vcpu_get_reg_timer() local
177 reg_val = riscv_timebase; in kvm_riscv_vcpu_get_reg_timer()
180 reg_val = kvm_riscv_current_cycles(gt); in kvm_riscv_vcpu_get_reg_timer()
183 reg_val = t->next_cycles; in kvm_riscv_vcpu_get_reg_timer()
186 reg_val = (t->next_set) ? KVM_RISCV_TIMER_STATE_ON : in kvm_riscv_vcpu_get_reg_timer()
208 u64 reg_val; in kvm_riscv_vcpu_set_reg_timer() local
221 if (reg_val != riscv_timebase) in kvm_riscv_vcpu_set_reg_timer()
225 gt->time_delta = reg_val - get_cycles64(); in kvm_riscv_vcpu_set_reg_timer()
228 t->next_cycles = reg_val; in kvm_riscv_vcpu_set_reg_timer()
231 if (reg_val == KVM_RISCV_TIMER_STATE_ON) in kvm_riscv_vcpu_set_reg_timer()
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A Dvcpu_vector.c183 unsigned long reg_val; in kvm_riscv_vcpu_set_reg_vector() local
185 if (copy_from_user(&reg_val, uaddr, reg_size)) in kvm_riscv_vcpu_set_reg_vector()
187 if (reg_val != cntx->vector.vlenb) in kvm_riscv_vcpu_set_reg_vector()
/arch/x86/hyperv/
A Dhv_apic.c39 u64 reg_val; in hv_apic_icr_read() local
41 rdmsrq(HV_X64_MSR_ICR, reg_val); in hv_apic_icr_read()
42 return reg_val; in hv_apic_icr_read()
47 u64 reg_val; in hv_apic_icr_write() local
49 reg_val = SET_XAPIC_DEST_FIELD(id); in hv_apic_icr_write()
50 reg_val = reg_val << 32; in hv_apic_icr_write()
51 reg_val |= low; in hv_apic_icr_write()
53 wrmsrq(HV_X64_MSR_ICR, reg_val); in hv_apic_icr_write()
58 u32 reg_val, hi; in hv_apic_read() local
64 return reg_val; in hv_apic_read()
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/arch/mips/kernel/
A Dtraps.c1837 unsigned int reg_val; in cache_parity_error() local
1842 reg_val = read_c0_cacheerr(); in cache_parity_error()
1851 reg_val & (1<<29) ? "ED " : "", in cache_parity_error()
1852 reg_val & (1<<28) ? "ET " : "", in cache_parity_error()
1853 reg_val & (1<<27) ? "ES " : "", in cache_parity_error()
1854 reg_val & (1<<26) ? "EE " : "", in cache_parity_error()
1855 reg_val & (1<<25) ? "EB " : "", in cache_parity_error()
1872 if (reg_val & (1<<22)) in cache_parity_error()
1875 if (reg_val & (1<<23)) in cache_parity_error()
1885 unsigned int reg_val; in do_ftlb() local
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/arch/mips/include/asm/
A Dmips-cps.h76 uint##sz##_t reg_val = read_##unit##_##name(); \
77 reg_val &= ~mask; \
78 reg_val |= val; \
79 write_##unit##_##name(reg_val); \
/arch/powerpc/platforms/pseries/
A Drtas-fadump.c307 static void __init rtas_fadump_set_regval(struct pt_regs *regs, u64 reg_id, u64 reg_val) in rtas_fadump_set_regval() argument
313 regs->gpr[i] = (unsigned long)reg_val; in rtas_fadump_set_regval()
315 regs->nip = (unsigned long)reg_val; in rtas_fadump_set_regval()
317 regs->msr = (unsigned long)reg_val; in rtas_fadump_set_regval()
319 regs->ctr = (unsigned long)reg_val; in rtas_fadump_set_regval()
321 regs->link = (unsigned long)reg_val; in rtas_fadump_set_regval()
323 regs->xer = (unsigned long)reg_val; in rtas_fadump_set_regval()
325 regs->ccr = (unsigned long)reg_val; in rtas_fadump_set_regval()
327 regs->dar = (unsigned long)reg_val; in rtas_fadump_set_regval()
329 regs->dsisr = (unsigned long)reg_val; in rtas_fadump_set_regval()
/arch/arm/plat-orion/
A Dgpio.c498 u32 reg_val; in orion_gpio_unmask_irq() local
502 reg_val = irq_reg_readl(gc, ct->regs.mask); in orion_gpio_unmask_irq()
503 reg_val |= mask; in orion_gpio_unmask_irq()
504 irq_reg_writel(gc, reg_val, ct->regs.mask); in orion_gpio_unmask_irq()
512 u32 reg_val; in orion_gpio_mask_irq() local
515 reg_val = irq_reg_readl(gc, ct->regs.mask); in orion_gpio_mask_irq()
516 reg_val &= ~mask; in orion_gpio_mask_irq()
517 irq_reg_writel(gc, reg_val, ct->regs.mask); in orion_gpio_mask_irq()
/arch/riscv/include/asm/
A Dkvm_vcpu_sbi.h89 unsigned long *reg_val);
91 unsigned long reg_val);
/arch/sparc/include/asm/
A Dhypervisor.h3446 unsigned long *reg_val);
3448 unsigned long reg_val);
3456 unsigned long *reg_val);
3458 unsigned long reg_val);
3467 unsigned long *reg_val);
3469 unsigned long reg_val);

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