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Searched refs:rt_sysc_r32 (Results 1 – 4 of 4) sorted by relevance

/arch/mips/pci/
A Dpci-rt3883.c307 rstctrl = rt_sysc_r32(RT3883_SYSC_REG_RSTCTRL); in rt3883_pci_preinit()
308 syscfg1 = rt_sysc_r32(RT3883_SYSC_REG_SYSCFG1); in rt3883_pci_preinit()
309 clkcfg1 = rt_sysc_r32(RT3883_SYSC_REG_CLKCFG1); in rt3883_pci_preinit()
320 t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0); in rt3883_pci_preinit()
324 t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN1); in rt3883_pci_preinit()
328 t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN1); in rt3883_pci_preinit()
332 t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0); in rt3883_pci_preinit()
382 t = rt_sysc_r32(RT3883_SYSC_REG_RSTCTRL); in rt3883_pci_preinit()
389 t = rt_sysc_r32(RT3883_SYSC_REG_CLKCFG1); in rt3883_pci_preinit()
393 t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0); in rt3883_pci_preinit()
A Dpci-mt7620.c243 if (!(rt_sysc_r32(PPLL_CFG1) & PPLL_LD)) { in mt7620_pci_hw_init()
/arch/mips/include/asm/mach-ralink/
A Dralink_regs.h40 static inline u32 rt_sysc_r32(unsigned reg) in rt_sysc_r32() function
47 u32 val = rt_sysc_r32(reg) & ~clr; in rt_sysc_m32()
A Dmt7620.h62 return rt_sysc_r32(SYSC_REG_CHIP_REV) & CHIP_REV_ECO_MASK; in mt7620_get_eco()

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