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/arch/arm/include/debug/
A Dicedcc.S15 .macro senduart, rd, rx
19 .macro busyuart, rd, rx
22 tst \rx, #0x20000000
35 tst \rx, #0x20000000
42 .macro senduart, rd, rx
46 .macro busyuart, rd, rx
49 tst \rx, #0x10000000
62 tst \rx, #0x10000000
69 .macro senduart, rd, rx
76 tst \rx, #2
[all …]
A D8250.S15 .macro store, rd, rx:vararg
17 str \rd, \rx
21 .macro load, rd, rx:vararg
22 ldr \rd, \rx
26 .macro store, rd, rx:vararg
27 strb \rd, \rx
30 .macro load, rd, rx:vararg
31 ldrb \rd, \rx
37 .macro senduart,rd,rx
41 .macro busyuart,rd,rx
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A Dsamsung.S12 .macro fifo_level_s5pv210 rd, rx
13 ldr \rd, [\rx, # S3C2410_UFSTAT]
18 .macro fifo_full_s5pv210 rd, rx
19 ldr \rd, [\rx, # S3C2410_UFSTAT]
27 .macro fifo_level_s3c2440 rd, rx
47 .macro senduart,rd,rx
51 .macro busyuart, rd, rx
58 fifo_full \rd, \rx
72 .macro waituartcts,rd,rx
75 .macro waituarttxrdy,rd,rx
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A Dmsm.S14 .macro senduart, rd, rx
17 str \rd, [\rx, #0x70]
20 .macro waituartcts,rd,rx
23 .macro waituarttxrdy, rd, rx
25 ldr \rd, [\rx, #0x08]
30 1001: ldr \rd, [\rx, #0x14]
38 str \rd, [\rx, #0x10]
42 str \rd, [\rx, #0x40]
44 ldr \rd, [\rx, #0x08]
47 .macro busyuart, rd, rx
A Drenesas-scif.S36 .macro waituartcts,rd,rx
39 .macro waituarttxrdy, rd, rx
40 1001: ldrh \rd, [\rx, #FSR]
45 .macro senduart, rd, rx
46 strb \rd, [\rx, #FTDR]
47 ldrh \rd, [\rx, #FSR]
49 strh \rd, [\rx, #FSR]
52 .macro busyuart, rd, rx
53 1001: ldrh \rd, [\rx, #FSR]
A Domap2plus.S63 .macro senduart,rd,rx
64 orr \rd, \rd, \rx, lsl #24 @ preserve LSR reg offset
65 bic \rx, \rx, #0xff @ get base (THR) reg address
66 strb \rd, [\rx] @ send lower byte of rd
67 orr \rx, \rx, \rd, lsr #24 @ restore original rx (LSR)
71 .macro busyuart,rd,rx
72 1001: ldrb \rd, [\rx] @ rx contains UART_LSR address
78 .macro waituartcts,rd,rx
81 .macro waituarttxrdy,rd,rx
A Dbcm63xx.S15 .macro senduart, rd, rx
17 strb \rd, [\rx, #UART_FIFO_REG]
20 .macro waituarttxrdy, rd, rx
21 1001: ldr \rd, [\rx, #UART_IR_REG]
26 .macro waituartcts, rd, rx
29 .macro busyuart, rd, rx
30 1002: ldr \rd, [\rx, #UART_IR_REG]
A Dmeson.S18 .macro senduart,rd,rx
19 str \rd, [\rx, #MESON_AO_UART_WFIFO]
22 .macro busyuart,rd,rx
23 1002: ldr \rd, [\rx, #MESON_AO_UART_STATUS]
28 .macro waituartcts,rd,rx
31 .macro waituarttxrdy,rd,rx
32 1001: ldr \rd, [\rx, #MESON_AO_UART_STATUS]
A Dpl01x.S18 .macro senduart,rd,rx
19 strb \rd, [\rx, #UART01x_DR]
22 .macro waituartcts,rd,rx
25 .macro waituarttxrdy,rd,rx
26 1001: ldr \rd, [\rx, #UART01x_FR]
32 .macro busyuart,rd,rx
33 1001: ldr \rd, [\rx, #UART01x_FR]
A Dsti.S22 .macro senduart,rd,rx
23 strb \rd, [\rx, #ASC_TX_BUF_OFF]
26 .macro waituartcts,rd,rx
29 .macro waituarttxrdy,rd,rx
30 1001: ldr \rd, [\rx, #ASC_STA_OFF]
35 .macro busyuart,rd,rx
36 1001: ldr \rd, [\rx, #ASC_STA_OFF]
A Dstm32.S26 .macro senduart,rd,rx
27 strb \rd, [\rx, #STM32_USART_TDR_OFF]
30 .macro waituartcts,rd,rx
33 .macro waituarttxrdy,rd,rx
34 1001: ldr \rd, [\rx, #(STM32_USART_SR_OFF)] @ Read Status Register
39 .macro busyuart,rd,rx
40 1001: ldr \rd, [\rx, #(STM32_USART_SR_OFF)] @ Read Status Register
A Dasm9260.S14 .macro waituarttxrdy,rd,rx
17 .macro waituartcts,rd,rx
20 .macro senduart,rd,rx
21 str \rd, [\rx, #0x50] @ TXDATA
24 .macro busyuart,rd,rx
25 1002: ldr \rd, [\rx, #0x60] @ STAT
A Ddigicolor.S20 .macro senduart,rd,rx
21 strb \rd, [\rx, #UA0_EMI_REC]
24 .macro waituartcts,rd,rx
27 .macro waituarttxrdy,rd,rx
30 .macro busyuart,rd,rx
31 1001: ldrb \rd, [\rx, #UA0_STATUS]
A Dat91.S18 .macro senduart,rd,rx
19 strb \rd, [\rx, #(AT91_DBGU_THR)] @ Write to Transmitter Holding Register
22 .macro waituarttxrdy,rd,rx
23 1001: ldr \rd, [\rx, #(AT91_DBGU_SR)] @ Read Status Register
28 .macro waituartcts,rd,rx
31 .macro busyuart,rd,rx
32 1001: ldr \rd, [\rx, #(AT91_DBGU_SR)] @ Read Status Register
A Dvt8500.S21 .macro senduart,rd,rx
22 strb \rd, [\rx, #0]
25 .macro busyuart,rd,rx
26 1001: ldr \rd, [\rx, #0x1c]
31 .macro waituartcts,rd,rx
34 .macro waituarttxrdy,rd,rx
A Dclps711x.S23 .macro waituartcts,rd,rx
26 .macro waituarttxrdy,rd,rx
29 .macro senduart,rd,rx
30 str \rd, [\rx, #UARTDR]
33 .macro busyuart,rd,rx
34 1001: ldr \rd, [\rx, #SYSFLG]
A Dzynq.S32 .macro senduart,rd,rx
33 strb \rd, [\rx, #UART_FIFO_OFFSET] @ TXDATA
36 .macro waituartcts,rd,rx
39 .macro waituarttxrdy,rd,rx
40 1001: ldr \rd, [\rx, #UART_SR_OFFSET]
46 .macro busyuart,rd,rx
47 1002: ldr \rd, [\rx, #UART_SR_OFFSET] @ get status register
A Ddc21285.S27 .macro senduart,rd,rx
28 str \rd, [\rx, #0x160] @ UARTDR
31 .macro busyuart,rd,rx
32 1001: ldr \rd, [\rx, #0x178] @ UARTFLG
37 .macro waituartcts,rd,rx
40 .macro waituarttxrdy,rd,rx
A Dimx.S33 .macro senduart,rd,rx
35 str \rd, [\rx, #0x40] @ TXDATA
38 .macro waituartcts,rd,rx
41 .macro waituarttxrdy,rd,rx
44 .macro busyuart,rd,rx
45 1002: ldr \rd, [\rx, #0x98] @ SR2
A Dvf.S22 .macro senduart, rd, rx
23 strb \rd, [\rx, #0x7] @ Data Register
26 .macro busyuart, rd, rx
27 1001: ldrb \rd, [\rx, #0x4] @ Status Register 1
32 .macro waituartcts,rd,rx
35 .macro waituarttxrdy,rd,rx
A Dsa1100.S50 .macro senduart,rd,rx
51 str \rd, [\rx, #UTDR]
54 .macro waituartcts,rd,rx
57 .macro waituarttxrdy,rd,rx
58 1001: ldr \rd, [\rx, #UTSR1]
63 .macro busyuart,rd,rx
64 1001: ldr \rd, [\rx, #UTSR1]
/arch/csky/abiv1/
A Dalignment.c15 return rx == 15 ? regs->lr : *((uint32_t *)&(regs->a0) - 2 + rx); in get_ptreg()
20 if (rx == 15) in put_ptreg()
23 *((uint32_t *)&(regs->a0) - 2 + rx) = val; in put_ptreg()
217 uint32_t rx = 0; in csky_alignment() local
253 rx = opcode & 0xf; in csky_alignment()
258 if (rx == 0 || rx == 1 || rz == 0 || rz == 1) in csky_alignment()
263 addr = get_ptreg(regs, rx) + (imm << 1); in csky_alignment()
267 addr = get_ptreg(regs, rx) + (imm << 2); in csky_alignment()
271 addr = get_ptreg(regs, rx) + (imm << 1); in csky_alignment()
275 addr = get_ptreg(regs, rx) + (imm << 2); in csky_alignment()
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/arch/s390/kernel/
A Duprobes.c265 union split_register *rx; in handle_insn_ril() local
272 rx = (union split_register *) &regs->gprs[insn->reg]; in handle_insn_ril()
280 rx->u64 = (unsigned long)uptr; in handle_insn_ril()
287 rc = emu_load_ril((u16 __user *)uptr, &rx->u32[1]); in handle_insn_ril()
290 rc = emu_load_ril((s16 __user *)uptr, &rx->u64); in handle_insn_ril()
293 rc = emu_load_ril((s16 __user *)uptr, &rx->u32[1]); in handle_insn_ril()
296 rc = emu_load_ril((u16 __user *)uptr, &rx->u64); in handle_insn_ril()
299 rc = emu_load_ril((u64 __user *)uptr, &rx->u64); in handle_insn_ril()
302 rc = emu_load_ril((s32 __user *)uptr, &rx->u64); in handle_insn_ril()
305 rc = emu_load_ril((u32 __user *)uptr, &rx->u32[1]); in handle_insn_ril()
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/arch/csky/abiv1/inc/abi/
A Dentry.h129 .macro RD_MIR rx
130 cprcr \rx, cpcr0
133 .macro RD_MEH rx
134 cprcr \rx, cpcr4
137 .macro RD_MCIR rx
138 cprcr \rx, cpcr8
141 .macro RD_PGDR rx
145 .macro WR_MEH rx
146 cpwcr \rx, cpcr4
149 .macro WR_MCIR rx
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/arch/riscv/boot/dts/starfive/
A Djh7110-starfive-visionfive-2-v1.3b.dts31 motorcomm,rx-clk-drv-microamp = <3970>;
32 motorcomm,rx-data-drv-microamp = <2910>;
33 rx-internal-delay-ps = <1500>;
40 motorcomm,rx-clk-drv-microamp = <3970>;
41 motorcomm,rx-data-drv-microamp = <2910>;
42 rx-internal-delay-ps = <300>;

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