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/arch/arm64/crypto/
A Dsm4-ce-asm.h12 sm4e b0.4s, v24.4s; \
13 sm4e b0.4s, v25.4s; \
14 sm4e b0.4s, v26.4s; \
15 sm4e b0.4s, v27.4s; \
16 sm4e b0.4s, v28.4s; \
17 sm4e b0.4s, v29.4s; \
18 sm4e b0.4s, v30.4s; \
19 sm4e b0.4s, v31.4s; \
20 rev64 b0.4s, b0.4s; \
29 sm4e b0.4s, v24.4s; \
[all …]
A Dsm4-ce-cipher-core.S20 ld1 {v0.4s-v3.4s}, [x0], #64
22 ld1 {v4.4s-v7.4s}, [x0]
23 sm4e v8.4s, v0.4s
24 sm4e v8.4s, v1.4s
25 sm4e v8.4s, v2.4s
26 sm4e v8.4s, v3.4s
27 sm4e v8.4s, v4.4s
28 sm4e v8.4s, v5.4s
29 sm4e v8.4s, v6.4s
30 sm4e v8.4s, v7.4s
[all …]
/arch/m68k/ifpsp060/
A DMISC34 freal.s : 2.4
40 x_foperr.s : 2.9
43 x_fdz.s : 2.5
44 x_fline.s : 2.5
46 fsin.s : 2.6
47 ftan.s : 2.6
48 fatan.s : 2.3
49 fasin.s : 2.3
50 facos.s : 2.5
51 fetox.s : 2.4
[all …]
/arch/mips/cavium-octeon/executive/
A Dcvmx-interrupt-decodes.c61 gmx_rx_int_en.s.hg2cc = 1; in __cvmx_interrupt_gmxx_rxx_int_en_enable()
62 gmx_rx_int_en.s.hg2fld = 1; in __cvmx_interrupt_gmxx_rxx_int_en_enable()
63 gmx_rx_int_en.s.undat = 1; in __cvmx_interrupt_gmxx_rxx_int_en_enable()
64 gmx_rx_int_en.s.uneop = 1; in __cvmx_interrupt_gmxx_rxx_int_en_enable()
65 gmx_rx_int_en.s.unsop = 1; in __cvmx_interrupt_gmxx_rxx_int_en_enable()
67 gmx_rx_int_en.s.bad_seq = 1; in __cvmx_interrupt_gmxx_rxx_int_en_enable()
77 gmx_rx_int_en.s.ovrerr = 1; in __cvmx_interrupt_gmxx_rxx_int_en_enable()
79 gmx_rx_int_en.s.skperr = 1; in __cvmx_interrupt_gmxx_rxx_int_en_enable()
80 gmx_rx_int_en.s.rcverr = 1; in __cvmx_interrupt_gmxx_rxx_int_en_enable()
83 gmx_rx_int_en.s.jabber = 1; in __cvmx_interrupt_gmxx_rxx_int_en_enable()
[all …]
A Dcvmx-helper-sgmii.c61 gmxx_prtx_cfg.s.en = 0; in __cvmx_helper_sgmii_hardware_init_one_time()
170 control_reg.s.an_en = 1; in __cvmx_helper_sgmii_hardware_init_link()
213 gmxx_prtx_cfg.s.en = 0; in __cvmx_helper_sgmii_hardware_init_link_speed()
243 pcsx_miscx_ctl_reg.s.gmxeno = !link_info.s.link_up; in __cvmx_helper_sgmii_hardware_init_link_speed()
247 gmxx_prtx_cfg.s.duplex = link_info.s.full_duplex; in __cvmx_helper_sgmii_hardware_init_link_speed()
352 mode.s.en = 1; in __cvmx_helper_sgmii_probe()
409 result.s.link_up = 1; in __cvmx_helper_sgmii_link_get()
411 result.s.speed = 1000; in __cvmx_helper_sgmii_link_get()
419 result.s.link_up = 1; in __cvmx_helper_sgmii_link_get()
463 result.s.link_up = in __cvmx_helper_sgmii_link_get()
[all …]
A Dcvmx-spi.c345 srxx_spi4_stat.s.m = 1; in cvmx_spi_calendar_setup_cb()
408 stxx_spi4_stat.s.m = 1; in cvmx_spi_calendar_setup_cb()
450 if (stat.s.s4clk0 && stat.s.s4clk1 && clock_transitions) { in cvmx_spi_clock_detect_cb()
457 stat.s.s4clk0 = 0; in cvmx_spi_clock_detect_cb()
458 stat.s.s4clk1 = 0; in cvmx_spi_clock_detect_cb()
464 } while (stat.s.s4clk0 == 0 || stat.s.s4clk1 == 0); in cvmx_spi_clock_detect_cb()
475 if (stat.s.d4clk0 && stat.s.d4clk1 && clock_transitions) { in cvmx_spi_clock_detect_cb()
482 stat.s.d4clk0 = 0; in cvmx_spi_clock_detect_cb()
483 stat.s.d4clk1 = 0; in cvmx_spi_clock_detect_cb()
489 } while (stat.s.d4clk0 == 0 || stat.s.d4clk1 == 0); in cvmx_spi_clock_detect_cb()
[all …]
A Dcvmx-pko.c132 config.s.ipid = port; in __cvmx_pko_port_map_o68()
146 config.s.ipid = port; in __cvmx_pko_port_map_o68()
148 config.s.crc = 1; in __cvmx_pko_port_map_o68()
149 config.s.min_pkt = 1; in __cvmx_pko_port_map_o68()
151 config.s.eid = config.s.intr; in __cvmx_pko_port_map_o68()
241 if (flags.s.ena_pko) in cvmx_pko_enable()
245 flags.s.ena_dwb = 1; in cvmx_pko_enable()
246 flags.s.ena_pko = 1; in cvmx_pko_enable()
251 flags.s.store_be = 1; in cvmx_pko_enable()
290 config.s.tail = 1; in cvmx_pko_shutdown()
[all …]
/arch/x86/kvm/
A Di8259.c77 if (s != &s->pics_state->pics[0]) in pic_clear_isr()
141 mask = s->irr & ~s->imr; in pic_get_irq()
151 if (s->special_fully_nested_mode && s == &s->pics_state->pics[0]) in pic_get_irq()
272 u8 edge_irr = s->irr & ~s->elcr; in kvm_pic_reset()
276 s->irr &= s->elcr; in kvm_pic_reset()
333 priority = get_priority(s, s->isr); in pic_ioport_write()
365 off = (s == &s->pics_state->pics[0]) ? 0 : 8; in pic_ioport_write()
442 s->elcr = val & s->elcr_mask; in elcr_ioport_write()
591 if (!s) in kvm_pic_init()
597 s->pics[0].pics_state = s; in kvm_pic_init()
[all …]
/arch/arm64/kernel/vdso/
A Dvgetrandom-chacha.S57 uzp1 one_v.4s, one_v.4s, one_v.4s
76 add state0.4s, state0.4s, state1.4s
81 add state2.4s, state2.4s, state3.4s
87 add state0.4s, state0.4s, state1.4s
93 add state2.4s, state2.4s, state3.4s
106 add state0.4s, state0.4s, state1.4s
111 add state2.4s, state2.4s, state3.4s
117 add state0.4s, state0.4s, state1.4s
139 add state0.4s, state0.4s, copy0.4s
141 add state1.4s, state1.4s, copy1.4s
[all …]
/arch/xtensa/variants/test_kc705_hifi/include/variant/
A Dtie.h115 #define XCHAL_NCP_SA_LIST(s) \ argument
124 XCHAL_SA_REG(s,0,0,0,1, scompare1, 4, 4, 4,0x020C, sr,12 , 32,0,0,0)
127 #define XCHAL_CP0_SA_LIST(s) /* empty */ argument
130 #define XCHAL_CP1_SA_LIST(s) \ argument
156 XCHAL_SA_REG(s,0,0,2,0, u3, 8, 8, 8,0x1023, u,3 , 64,0,0,0)
159 #define XCHAL_CP2_SA_LIST(s) /* empty */ argument
162 #define XCHAL_CP3_SA_LIST(s) /* empty */ argument
165 #define XCHAL_CP4_SA_LIST(s) /* empty */ argument
168 #define XCHAL_CP5_SA_LIST(s) /* empty */ argument
171 #define XCHAL_CP6_SA_LIST(s) /* empty */ argument
[all …]
/arch/alpha/lib/
A Dmemcpy.c32 d++; s++; \
38 d--; s--; \
50 d++; s++; \
55 d--; s--; \
63 #define DO_REST_ALIGNED_UP(d,s,n) DO_REST_UP(d,s,n) argument
64 #define DO_REST_ALIGNED_DN(d,s,n) DO_REST_DN(d,s,n) argument
91 s += 8; in __memcpy_unaligned_up()
105 s += n; in __memcpy_unaligned_dn()
128 s += 8; in __memcpy_aligned_up()
138 s += n; in __memcpy_aligned_dn()
[all …]
/arch/xtensa/variants/test_kc705_be/include/variant/
A Dtie.h115 #define XCHAL_NCP_SA_LIST(s) \ argument
124 XCHAL_SA_REG(s,0,0,0,1, m3, 4, 4, 4,0x0223, sr,35 , 32,0,0,0)
127 #define XCHAL_CP0_SA_LIST(s) /* empty */ argument
130 #define XCHAL_CP1_SA_LIST(s) \ argument
148 XCHAL_SA_REG(s,0,0,2,0, aeq3, 8, 8, 8,0x006B, aeq,3 , 56,0,0,0)
151 #define XCHAL_CP2_SA_LIST(s) /* empty */ argument
154 #define XCHAL_CP3_SA_LIST(s) /* empty */ argument
157 #define XCHAL_CP4_SA_LIST(s) /* empty */ argument
160 #define XCHAL_CP5_SA_LIST(s) /* empty */ argument
163 #define XCHAL_CP6_SA_LIST(s) /* empty */ argument
[all …]
/arch/arm/boot/compressed/
A Dstring.c36 *d++ = *s++; in memcpy()
37 *d++ = *s++; in memcpy()
38 *d++ = *s++; in memcpy()
39 *d++ = *s++; in memcpy()
40 *d++ = *s++; in memcpy()
41 *d++ = *s++; in memcpy()
42 *d++ = *s++; in memcpy()
43 *d++ = *s++; in memcpy()
47 *d++ = *s++; in memcpy()
149 last = s; in strrchr()
[all …]
/arch/xtensa/variants/test_mmuhifi_c3/include/variant/
A Dtie.h92 #define XCHAL_NCP_SA_LIST(s) \ argument
95 XCHAL_SA_REG(s,1,2,1,1, threadptr, 4, 4, 4,0x03E7, ur,231, 32,0,0,0)
98 #define XCHAL_CP0_SA_LIST(s) /* empty */ argument
101 #define XCHAL_CP1_SA_LIST(s) \ argument
117 XCHAL_SA_REG(s,0,0,2,0, aeq3, 8, 8, 8,0x006B, aeq,3 , 56,0,0,0)
120 #define XCHAL_CP2_SA_LIST(s) /* empty */ argument
123 #define XCHAL_CP3_SA_LIST(s) /* empty */ argument
126 #define XCHAL_CP4_SA_LIST(s) /* empty */ argument
129 #define XCHAL_CP5_SA_LIST(s) /* empty */ argument
132 #define XCHAL_CP6_SA_LIST(s) /* empty */ argument
[all …]
/arch/loongarch/kvm/intc/
A Dpch_pic.c21 if (mask & s->irr & ~s->mask) { in pch_pic_update_irq()
22 s->isr |= mask; in pch_pic_update_irq()
27 if (mask & s->isr & ~s->irr) { in pch_pic_update_irq()
28 s->isr &= ~mask; in pch_pic_update_irq()
87 u64 val = *s; in pch_pic_read_reg()
193 if (!s) { in kvm_pch_pic_read()
305 if (!s) { in kvm_pch_pic_write()
388 p = &s->irr; in kvm_pch_pic_regs_access()
391 p = &s->isr; in kvm_pch_pic_regs_access()
493 if (!s) in kvm_pch_pic_create()
[all …]
A Deiointc.c245 data = s->enable.reg_u64[index] & ~old & s->isr.reg_u64[index]; in loongarch_eiointc_write()
255 data = ~s->enable.reg_u64[index] & old & s->isr.reg_u64[index]; in loongarch_eiointc_write()
438 s->num_cpu = val; in kvm_eiointc_ctrl_access()
548 p = &s->num_cpu; in kvm_eiointc_sw_status_access()
554 p = &s->features; in kvm_eiointc_sw_status_access()
557 p = &s->status; in kvm_eiointc_sw_status_access()
616 if (!s) in kvm_eiointc_create()
620 s->kvm = kvm; in kvm_eiointc_create()
625 device = &s->device; in kvm_eiointc_create()
632 kfree(s); in kvm_eiointc_create()
[all …]
/arch/powerpc/platforms/powernv/
A Dvas-debug.c67 print_reg(s, window, VREG(LPID)); in hvwc_show()
68 print_reg(s, window, VREG(PID)); in hvwc_show()
69 print_reg(s, window, VREG(XLATE_MSR)); in hvwc_show()
71 print_reg(s, window, VREG(XLATE_CTL)); in hvwc_show()
72 print_reg(s, window, VREG(AMR)); in hvwc_show()
73 print_reg(s, window, VREG(SEIDR)); in hvwc_show()
77 print_reg(s, window, VREG(PSWID)); in hvwc_show()
78 print_reg(s, window, VREG(LFIFO_BAR)); in hvwc_show()
84 print_reg(s, window, VREG(LRX_WCRED)); in hvwc_show()
86 print_reg(s, window, VREG(TX_WCRED)); in hvwc_show()
[all …]
/arch/mips/include/asm/octeon/
A Dcvmx-ipd.h102 size.s.mb_size = mbuff_size; in cvmx_ipd_config()
133 if (ipd_reg.s.ipd_en) { in cvmx_ipd_enable()
137 ipd_reg.s.ipd_en = 1; in cvmx_ipd_enable()
140 ipd_reg.s.len_m8 = TRUE; in cvmx_ipd_enable()
152 ipd_reg.s.ipd_en = 0; in cvmx_ipd_disable()
172 if (ipd_ctl_status.s.no_wptr) in cvmx_ipd_free_ptr()
177 if (ipd_ptr_count.s.wqev_cnt) { in cvmx_ipd_free_ptr()
193 if (ipd_ptr_count.s.wqe_pcnt) { in cvmx_ipd_free_ptr()
313 s.ptr << 7), in cvmx_ipd_free_ptr()
325 ipd_ctl_status.s.reset = 1; in cvmx_ipd_free_ptr()
[all …]
/arch/powerpc/platforms/cell/
A Dspu_callbacks.c43 long spu_sys_callback(struct spu_syscall_block *s) in spu_sys_callback() argument
47 if (s->nr_ret >= ARRAY_SIZE(spu_syscall_table)) { in spu_sys_callback()
48 pr_debug("%s: invalid syscall #%lld", __func__, s->nr_ret); in spu_sys_callback()
52 syscall = spu_syscall_table[s->nr_ret]; in spu_sys_callback()
57 s->nr_ret, in spu_sys_callback()
58 s->parm[0], s->parm[1], s->parm[2], in spu_sys_callback()
59 s->parm[3], s->parm[4], s->parm[5]); in spu_sys_callback()
61 return syscall(s->parm[0], s->parm[1], s->parm[2], in spu_sys_callback()
62 s->parm[3], s->parm[4], s->parm[5]); in spu_sys_callback()
/arch/mips/pci/
A Dpci-octeon.c57 } s; member
264 pci_addr.s.io = 1; in octeon_read_config()
265 pci_addr.s.did = 3; in octeon_read_config()
298 pci_addr.s.io = 1; in octeon_write_config()
299 pci_addr.s.did = 3; in octeon_write_config()
422 pci_clock = (cnt_reg_end.s.pcicnt - cnt_reg_start.s.pcicnt) / in octeon_pci_initialize()
449 cfg19.s.tdomc = 4; in octeon_pci_initialize()
461 cfg19.s.mdrrmc = 2; in octeon_pci_initialize()
473 cfg19.s.mrbcm = 1; in octeon_pci_initialize()
517 cfg22.s.mrv = 0xff; in octeon_pci_initialize()
[all …]
/arch/x86/kernel/
A Dearly_printk.c130 s++; in early_serial_write()
164 ++s; in early_serial_init()
180 s += strcspn(s, ","); in early_serial_init()
182 s++; in early_serial_init()
226 s++; in early_mmio_serial_init()
236 s += strcspn(s, ","); in early_mmio_serial_init()
238 s++; in early_mmio_serial_init()
273 ++s; in early_pci_serial_init()
291 ++s; in early_pci_serial_init()
296 ++s; in early_pci_serial_init()
[all …]
/arch/s390/include/asm/
A Dstring.h55 #define strlen(s) __strlen(s) argument
104 const void *ret = s + n; in memchr()
113 : [ret] "+&a" (ret), [s] "+&a" (s) in memchr()
123 const void *ret = s + n; in memscan()
129 : [ret] "+&a" (ret), [s] "+&a" (s) in memscan()
159 const char *tmp = s; in __no_sanitize_prefix_strfunc()
168 return end - (unsigned long)s; in __no_sanitize_prefix_strfunc()
175 const char *tmp = s; in strnlen()
176 const char *end = s + n; in strnlen()
185 return end - s; in strnlen()
[all …]
/arch/x86/boot/
A Dstring.c155 return sc - s; in strlen()
228 if (_tolower(s[1]) == 'x' && isxdigit(s[2])) in _parse_integer_fixup_radix()
235 if (*base == 16 && s[0] == '0' && _tolower(s[1]) == 'x') in _parse_integer_fixup_radix()
236 s += 2; in _parse_integer_fixup_radix()
237 return s; in _parse_integer_fixup_radix()
281 s++; in _parse_integer()
292 s = _parse_integer_fixup_radix(s, &base); in _kstrtoull()
298 s += rv; in _kstrtoull()
300 s++; in _kstrtoull()
301 if (*s) in _kstrtoull()
[all …]
/arch/xtensa/variants/csp/include/variant/
A Dtie.h112 #define XCHAL_NCP_SA_LIST(s) \ argument
113 XCHAL_SA_REG(s,1,2,1,1, threadptr, 4, 4, 4,0x03E7, ur,231, 32,0,0,0) \
121 XCHAL_SA_REG(s,0,0,0,1, m3, 4, 4, 4,0x0223, sr,35 , 32,0,0,0)
124 #define XCHAL_CP0_SA_LIST(s) /* empty */ argument
127 #define XCHAL_CP1_SA_LIST(s) /* empty */ argument
130 #define XCHAL_CP2_SA_LIST(s) /* empty */ argument
133 #define XCHAL_CP3_SA_LIST(s) /* empty */ argument
136 #define XCHAL_CP4_SA_LIST(s) /* empty */ argument
139 #define XCHAL_CP5_SA_LIST(s) /* empty */ argument
142 #define XCHAL_CP6_SA_LIST(s) /* empty */ argument
[all …]
/arch/openrisc/lib/
A Dmemcpy.c69 *d++ = *s++; in memcpy()
70 *d++ = *s++; in memcpy()
71 *d++ = *s++; in memcpy()
72 *d++ = *s++; in memcpy()
73 *d++ = *s++; in memcpy()
74 *d++ = *s++; in memcpy()
75 *d++ = *s++; in memcpy()
88 *d++ = *s++; in memcpy()
89 *d++ = *s++; in memcpy()
93 *d++ = *s++; in memcpy()
[all …]

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