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/arch/arm64/boot/dts/amd/
A Damd-seattle-cpus.dtsi51 i-cache-sets = <256>;
54 d-cache-sets = <256>;
67 i-cache-sets = <256>;
70 d-cache-sets = <256>;
82 i-cache-sets = <256>;
85 d-cache-sets = <256>;
168 cache-sets = <1024>;
176 cache-sets = <1024>;
184 cache-sets = <1024>;
192 cache-sets = <1024>;
[all …]
/arch/arm64/boot/dts/amazon/
A Dalpine-v3.dtsi30 d-cache-sets = <256>;
33 i-cache-sets = <256>;
44 d-cache-sets = <256>;
47 i-cache-sets = <256>;
58 d-cache-sets = <256>;
61 i-cache-sets = <256>;
72 d-cache-sets = <256>;
75 i-cache-sets = <256>;
86 d-cache-sets = <256>;
89 i-cache-sets = <256>;
[all …]
/arch/mips/mm/
A Dc-octeon.c183 c->icache.sets = 64 << ((config1 >> 22) & 7); in probe_octeon()
187 c->icache.sets * c->icache.ways * c->icache.linesz; in probe_octeon()
191 c->dcache.sets = 2; /* CN5XXX has two Dcache sets */ in probe_octeon()
193 c->dcache.sets = 1; /* CN3XXX has one Dcache set */ in probe_octeon()
196 c->dcache.sets * c->dcache.ways * c->dcache.linesz; in probe_octeon()
203 c->icache.sets = 8; in probe_octeon()
210 c->dcache.sets = 8; in probe_octeon()
217 c->icache.sets = 16; in probe_octeon()
224 c->dcache.sets = 8; in probe_octeon()
247 c->icache.ways, c->icache.sets, c->icache.linesz); in probe_octeon()
[all …]
A Dsc-mips.c153 unsigned long sets, line_sz, assoc; in mips_sc_probe_cm3() local
158 sets = cfg & CM_GCR_L2_CONFIG_SET_SIZE; in mips_sc_probe_cm3()
159 sets >>= __ffs(CM_GCR_L2_CONFIG_SET_SIZE); in mips_sc_probe_cm3()
160 if (sets) in mips_sc_probe_cm3()
161 c->scache.sets = 64 << sets; in mips_sc_probe_cm3()
171 c->scache.waysize = c->scache.sets * c->scache.linesz; in mips_sc_probe_cm3()
214 c->scache.sets = 64 << tmp; in mips_sc_probe()
241 c->scache.sets = 256; in mips_sc_probe()
247 c->scache.waysize = c->scache.sets * c->scache.linesz; in mips_sc_probe()
/arch/arm64/boot/dts/ti/
A Dk3-j784s4.dtsi65 i-cache-sets = <256>;
68 d-cache-sets = <256>;
79 i-cache-sets = <256>;
82 d-cache-sets = <256>;
93 i-cache-sets = <256>;
96 d-cache-sets = <256>;
107 i-cache-sets = <256>;
110 d-cache-sets = <256>;
121 i-cache-sets = <256>;
124 d-cache-sets = <256>;
[all …]
A Dk3-am654.dtsi43 i-cache-sets = <256>;
46 d-cache-sets = <128>;
57 i-cache-sets = <256>;
60 d-cache-sets = <128>;
71 i-cache-sets = <256>;
74 d-cache-sets = <128>;
85 i-cache-sets = <256>;
88 d-cache-sets = <128>;
99 cache-sets = <512>;
109 cache-sets = <512>;
A Dk3-j742s2.dtsi47 i-cache-sets = <256>;
50 d-cache-sets = <256>;
61 i-cache-sets = <256>;
64 d-cache-sets = <256>;
75 i-cache-sets = <256>;
78 d-cache-sets = <256>;
89 i-cache-sets = <256>;
92 d-cache-sets = <256>;
A Dk3-am625.dtsi46 i-cache-sets = <256>;
49 d-cache-sets = <128>;
63 i-cache-sets = <256>;
66 d-cache-sets = <128>;
80 i-cache-sets = <256>;
83 d-cache-sets = <128>;
97 i-cache-sets = <256>;
100 d-cache-sets = <128>;
157 cache-sets = <512>;
A Dk3-am62a7.dtsi46 i-cache-sets = <256>;
49 d-cache-sets = <128>;
63 i-cache-sets = <256>;
66 d-cache-sets = <128>;
80 i-cache-sets = <256>;
83 d-cache-sets = <128>;
97 i-cache-sets = <256>;
100 d-cache-sets = <128>;
157 cache-sets = <512>;
A Dk3-am62p5.dtsi45 i-cache-sets = <256>;
48 d-cache-sets = <128>;
62 i-cache-sets = <256>;
65 d-cache-sets = <128>;
79 i-cache-sets = <256>;
82 d-cache-sets = <128>;
96 i-cache-sets = <256>;
99 d-cache-sets = <128>;
156 cache-sets = <512>;
A Dk3-am642.dtsi36 i-cache-sets = <256>;
39 d-cache-sets = <128>;
50 i-cache-sets = <256>;
53 d-cache-sets = <128>;
64 cache-sets = <256>;
A Dk3-am652.dtsi33 i-cache-sets = <256>;
36 d-cache-sets = <128>;
47 i-cache-sets = <256>;
50 d-cache-sets = <128>;
61 cache-sets = <512>;
/arch/riscv/boot/dts/sophgo/
A Dsg2042-cpus.dtsi269 i-cache-sets = <512>;
272 d-cache-sets = <512>;
296 i-cache-sets = <512>;
299 d-cache-sets = <512>;
323 i-cache-sets = <512>;
326 d-cache-sets = <512>;
350 i-cache-sets = <512>;
353 d-cache-sets = <512>;
377 i-cache-sets = <512>;
380 d-cache-sets = <512>;
[all …]
A Dsg2044-cpus.dtsi20 i-cache-sets = <512>;
23 d-cache-sets = <512>;
56 i-cache-sets = <512>;
59 d-cache-sets = <512>;
92 i-cache-sets = <512>;
95 d-cache-sets = <512>;
128 i-cache-sets = <512>;
131 d-cache-sets = <512>;
164 i-cache-sets = <512>;
167 d-cache-sets = <512>;
[all …]
/arch/arm64/boot/dts/freescale/
A Dimx943.dtsi38 i-cache-sets = <128>;
41 d-cache-sets = <128>;
56 i-cache-sets = <128>;
59 d-cache-sets = <128>;
74 i-cache-sets = <128>;
77 d-cache-sets = <128>;
103 cache-sets = <256>;
113 cache-sets = <256>;
123 cache-sets = <256>;
133 cache-sets = <256>;
[all …]
/arch/arm64/boot/dts/marvell/
A Darmada-ap806-quad.dtsi24 i-cache-sets = <256>;
27 d-cache-sets = <256>;
39 i-cache-sets = <256>;
42 d-cache-sets = <256>;
54 i-cache-sets = <256>;
57 d-cache-sets = <256>;
69 i-cache-sets = <256>;
72 d-cache-sets = <256>;
80 cache-sets = <512>;
89 cache-sets = <512>;
A Darmada-ap807-quad.dtsi24 i-cache-sets = <256>;
27 d-cache-sets = <256>;
39 i-cache-sets = <256>;
42 d-cache-sets = <256>;
54 i-cache-sets = <256>;
57 d-cache-sets = <256>;
69 i-cache-sets = <256>;
72 d-cache-sets = <256>;
80 cache-sets = <512>;
89 cache-sets = <512>;
A Darmada-ap806-dual.dtsi24 i-cache-sets = <256>;
27 d-cache-sets = <256>;
39 i-cache-sets = <256>;
42 d-cache-sets = <256>;
50 cache-sets = <512>;
/arch/openrisc/kernel/
A Dcacheinfo.c23 this_leaf->number_of_sets = cache->sets; in ci_leaf_init()
46 cpuinfo->dcache.sets = 1 << ((dccfgr & SPR_DCCFGR_NCS) >> 3); in init_cache_level()
49 cpuinfo->dcache.sets * cpuinfo->dcache.ways * cpuinfo->dcache.block_size; in init_cache_level()
54 cpuinfo->dcache.sets, cpuinfo->dcache.ways); in init_cache_level()
61 cpuinfo->icache.sets = 1 << ((iccfgr & SPR_ICCFGR_NCS) >> 3); in init_cache_level()
64 cpuinfo->icache.sets * cpuinfo->icache.ways * cpuinfo->icache.block_size; in init_cache_level()
69 cpuinfo->icache.sets, cpuinfo->icache.ways); in init_cache_level()
/arch/arm/boot/dts/broadcom/
A Dbcm2836.dtsi43 /* Source for d/i-cache-line-size and d/i-cache-sets
58 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
61 i-cache-sets = <512>; // 32KiB(size)/32(line-size)=1024ways/2-way set
72 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
75 i-cache-sets = <512>; // 32KiB(size)/32(line-size)=1024ways/2-way set
86 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
89 i-cache-sets = <512>; // 32KiB(size)/32(line-size)=1024ways/2-way set
100 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
103 i-cache-sets = <512>; // 32KiB(size)/32(line-size)=1024ways/2-way set
107 /* Source for cache-line-size + cache-sets
[all …]
A Dbcm2837.dtsi42 /* Source for d/i-cache-line-size and d/i-cache-sets
57 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
60 i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
72 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
75 i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
87 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
90 i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
102 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
105 i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
109 /* Source for cache-line-size + cache-sets
[all …]
/arch/arm64/boot/dts/arm/
A Djuno-r1.dts95 i-cache-sets = <256>;
98 d-cache-sets = <256>;
112 i-cache-sets = <256>;
115 d-cache-sets = <256>;
129 i-cache-sets = <256>;
132 d-cache-sets = <128>;
146 i-cache-sets = <256>;
149 d-cache-sets = <128>;
163 i-cache-sets = <256>;
195 cache-sets = <2048>;
[all …]
A Djuno-r2.dts95 i-cache-sets = <256>;
98 d-cache-sets = <256>;
113 i-cache-sets = <256>;
116 d-cache-sets = <256>;
131 i-cache-sets = <256>;
134 d-cache-sets = <128>;
149 i-cache-sets = <256>;
152 d-cache-sets = <128>;
167 i-cache-sets = <256>;
201 cache-sets = <2048>;
[all …]
A Djuno.dts94 i-cache-sets = <256>;
97 d-cache-sets = <256>;
112 i-cache-sets = <256>;
115 d-cache-sets = <256>;
130 i-cache-sets = <256>;
133 d-cache-sets = <128>;
148 i-cache-sets = <256>;
151 d-cache-sets = <128>;
166 i-cache-sets = <256>;
200 cache-sets = <2048>;
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/arch/riscv/boot/dts/sifive/
A Dfu540-c000.dtsi29 i-cache-sets = <128>;
46 d-cache-sets = <64>;
48 d-tlb-sets = <1>;
52 i-cache-sets = <64>;
54 i-tlb-sets = <1>;
75 d-tlb-sets = <1>;
81 i-tlb-sets = <1>;
102 d-tlb-sets = <1>;
108 i-tlb-sets = <1>;
129 d-tlb-sets = <1>;
[all …]

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