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/arch/parisc/include/asm/
A Duaccess.h23 #define LDD_USER(sr, val, ptr) __get_user_asm64(sr, val, ptr) argument
24 #define STD_USER(sr, x, ptr) __put_user_asm64(sr, x, ptr) argument
26 #define LDD_USER(sr, val, ptr) __get_user_asm(sr, val, "ldd", ptr) argument
27 #define STD_USER(sr, x, ptr) __put_user_asm(sr, "std", x, ptr) argument
30 #define __get_user_internal(sr, val, ptr) \ argument
38 case 8: LDD_USER(sr, val, ptr); break; \
51 : "i"(sr), "r"(ptr), "i"(PRIV_USER), \
73 : "i"(sr), "r"(ptr)); \
106 : "i"(sr), "r"(ptr)); \
164 : "r"(x), "i"(sr), "r"(ptr))
[all …]
A Dcache.h52 #define pdtlb(sr, addr) asm volatile("pdtlb 0(%%sr%0,%1)" \ argument
54 : : "i"(sr), "r" (addr) : "memory")
55 #define pitlb(sr, addr) asm volatile("pitlb 0(%%sr%0,%1)" \ argument
58 : : "i"(sr), "r" (addr) : "memory")
A Dprocessor.h139 .sr = { 0, }, \
251 regs->sr[2] = LINUX_GATEWAY_SPACE; \
252 regs->sr[3] = 0xffff; \
253 regs->sr[4] = spaceid; \
254 regs->sr[5] = spaceid; \
255 regs->sr[6] = spaceid; \
256 regs->sr[7] = spaceid; \
/arch/mips/alchemy/devboards/
A Dplatform.c81 struct resource *sr; in db1x_register_pcmcia_socket() local
91 if (!sr) in db1x_register_pcmcia_socket()
115 sr[3].name = "insert"; in db1x_register_pcmcia_socket()
117 sr[3].start = sr[3].end = cd_irq; in db1x_register_pcmcia_socket()
119 sr[4].name = "card"; in db1x_register_pcmcia_socket()
121 sr[4].start = sr[4].end = card_irq; in db1x_register_pcmcia_socket()
127 sr[i].start = sr[i].end = stschg_irq; in db1x_register_pcmcia_socket()
131 sr[i].name = "eject"; in db1x_register_pcmcia_socket()
133 sr[i].start = sr[i].end = eject_irq; in db1x_register_pcmcia_socket()
136 pd->resource = sr; in db1x_register_pcmcia_socket()
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/arch/arm/mach-omap2/
A Dsmartreflex-class3.c15 static int sr_class3_enable(struct omap_sr *sr) in sr_class3_enable() argument
17 unsigned long volt = voltdm_get_voltage(sr->voltdm); in sr_class3_enable()
21 __func__, sr->name); in sr_class3_enable()
25 omap_vp_enable(sr->voltdm); in sr_class3_enable()
26 return sr_enable(sr, volt); in sr_class3_enable()
31 sr_disable_errgen(sr); in sr_class3_disable()
32 omap_vp_disable(sr->voltdm); in sr_class3_disable()
33 sr_disable(sr); in sr_class3_disable()
35 voltdm_reset(sr->voltdm); in sr_class3_disable()
40 static int sr_class3_configure(struct omap_sr *sr) in sr_class3_configure() argument
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/arch/xtensa/variants/csp/include/variant/
A Dtie.h114 XCHAL_SA_REG(s,1,0,0,1, acclo, 4, 4, 4,0x0210, sr,16 , 32,0,0,0) \
115 XCHAL_SA_REG(s,1,0,0,1, acchi, 4, 4, 4,0x0211, sr,17 , 8,0,0,0) \
116 XCHAL_SA_REG(s,0,0,0,1, br, 4, 4, 4,0x0204, sr,4 , 16,0,0,0) \
117 XCHAL_SA_REG(s,0,0,0,1, scompare1, 4, 4, 4,0x020C, sr,12 , 32,0,0,0) \
118 XCHAL_SA_REG(s,0,0,0,1, m0, 4, 4, 4,0x0220, sr,32 , 32,0,0,0) \
119 XCHAL_SA_REG(s,0,0,0,1, m1, 4, 4, 4,0x0221, sr,33 , 32,0,0,0) \
120 XCHAL_SA_REG(s,0,0,0,1, m2, 4, 4, 4,0x0222, sr,34 , 32,0,0,0) \
121 XCHAL_SA_REG(s,0,0,0,1, m3, 4, 4, 4,0x0223, sr,35 , 32,0,0,0)
/arch/xtensa/variants/de212/include/variant/
A Dtie.h90 XCHAL_SA_REG(s,1,0,0,1, acclo, 4, 4, 4,0x0210, sr,16 , 32,0,0,0) \
91 XCHAL_SA_REG(s,1,0,0,1, acchi, 4, 4, 4,0x0211, sr,17 , 8,0,0,0) \
92 XCHAL_SA_REG(s,0,0,0,1, scompare1, 4, 4, 4,0x020C, sr,12 , 32,0,0,0) \
93 XCHAL_SA_REG(s,0,0,0,1, m0, 4, 4, 4,0x0220, sr,32 , 32,0,0,0) \
94 XCHAL_SA_REG(s,0,0,0,1, m1, 4, 4, 4,0x0221, sr,33 , 32,0,0,0) \
95 XCHAL_SA_REG(s,0,0,0,1, m2, 4, 4, 4,0x0222, sr,34 , 32,0,0,0) \
96 XCHAL_SA_REG(s,0,0,0,1, m3, 4, 4, 4,0x0223, sr,35 , 32,0,0,0)
/arch/parisc/kernel/
A Dkgdb.c72 gr->sr0 = regs->sr[0]; in pt_regs_to_gdb_regs()
73 gr->sr1 = regs->sr[1]; in pt_regs_to_gdb_regs()
74 gr->sr2 = regs->sr[2]; in pt_regs_to_gdb_regs()
75 gr->sr3 = regs->sr[3]; in pt_regs_to_gdb_regs()
76 gr->sr4 = regs->sr[4]; in pt_regs_to_gdb_regs()
77 gr->sr5 = regs->sr[5]; in pt_regs_to_gdb_regs()
78 gr->sr6 = regs->sr[6]; in pt_regs_to_gdb_regs()
79 gr->sr7 = regs->sr[7]; in pt_regs_to_gdb_regs()
103 regs->sr[0] = gr->sr0; in gdb_regs_to_pt_regs()
104 regs->sr[1] = gr->sr1; in gdb_regs_to_pt_regs()
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A Dptrace.c449 case RI(sr[0]) ... RI(sr[7]): return regs->sr[num - RI(sr[0])]; in get_reg()
505 case RI(sr[0]) ... RI(sr[7]): return regs->sr[num - RI(sr[0])]; in set_reg()
705 REG_OFFSET_INDEX(sr,0),
706 REG_OFFSET_INDEX(sr,1),
707 REG_OFFSET_INDEX(sr,2),
708 REG_OFFSET_INDEX(sr,3),
709 REG_OFFSET_INDEX(sr,4),
710 REG_OFFSET_INDEX(sr,5),
711 REG_OFFSET_INDEX(sr,6),
712 REG_OFFSET_INDEX(sr,7),
A Dasm-offsets.c114 DEFINE(TASK_PT_SR0, offsetof(struct task_struct, thread.regs.sr[ 0])); in main()
115 DEFINE(TASK_PT_SR1, offsetof(struct task_struct, thread.regs.sr[ 1])); in main()
116 DEFINE(TASK_PT_SR2, offsetof(struct task_struct, thread.regs.sr[ 2])); in main()
199 DEFINE(PT_SR0, offsetof(struct pt_regs, sr[ 0])); in main()
200 DEFINE(PT_SR1, offsetof(struct pt_regs, sr[ 1])); in main()
201 DEFINE(PT_SR2, offsetof(struct pt_regs, sr[ 2])); in main()
202 DEFINE(PT_SR3, offsetof(struct pt_regs, sr[ 3])); in main()
203 DEFINE(PT_SR4, offsetof(struct pt_regs, sr[ 4])); in main()
204 DEFINE(PT_SR5, offsetof(struct pt_regs, sr[ 5])); in main()
205 DEFINE(PT_SR6, offsetof(struct pt_regs, sr[ 6])); in main()
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/arch/xtensa/variants/dc232b/include/variant/
A Dtie.h94 XCHAL_SA_REG(s,1,0,0,1, acclo, 4, 4, 4,0x0210, sr,16 , 32,0,0,0) \
95 XCHAL_SA_REG(s,1,0,0,1, acchi, 4, 4, 4,0x0211, sr,17 , 8,0,0,0) \
96 XCHAL_SA_REG(s,0,0,0,1, m0, 4, 4, 4,0x0220, sr,32 , 32,0,0,0) \
97 XCHAL_SA_REG(s,0,0,0,1, m1, 4, 4, 4,0x0221, sr,33 , 32,0,0,0) \
98 XCHAL_SA_REG(s,0,0,0,1, m2, 4, 4, 4,0x0222, sr,34 , 32,0,0,0) \
99 XCHAL_SA_REG(s,0,0,0,1, m3, 4, 4, 4,0x0223, sr,35 , 32,0,0,0) \
100 XCHAL_SA_REG(s,0,0,0,1, scompare1, 4, 4, 4,0x020C, sr,12 , 32,0,0,0) \
/arch/xtensa/variants/dc233c/include/variant/
A Dtie.h114 XCHAL_SA_REG(s,1,0,0,1, acclo, 4, 4, 4,0x0210, sr,16 , 32,0,0,0) \
115 XCHAL_SA_REG(s,1,0,0,1, acchi, 4, 4, 4,0x0211, sr,17 , 8,0,0,0) \
116 XCHAL_SA_REG(s,0,0,0,1, m0, 4, 4, 4,0x0220, sr,32 , 32,0,0,0) \
117 XCHAL_SA_REG(s,0,0,0,1, m1, 4, 4, 4,0x0221, sr,33 , 32,0,0,0) \
118 XCHAL_SA_REG(s,0,0,0,1, m2, 4, 4, 4,0x0222, sr,34 , 32,0,0,0) \
119 XCHAL_SA_REG(s,0,0,0,1, m3, 4, 4, 4,0x0223, sr,35 , 32,0,0,0) \
120 XCHAL_SA_REG(s,0,0,0,1, scompare1, 4, 4, 4,0x020C, sr,12 , 32,0,0,0)
/arch/xtensa/variants/test_kc705_be/include/variant/
A Dtie.h117 XCHAL_SA_REG(s,1,0,0,1, acclo, 4, 4, 4,0x0210, sr,16 , 32,0,0,0) \
118 XCHAL_SA_REG(s,1,0,0,1, acchi, 4, 4, 4,0x0211, sr,17 , 8,0,0,0) \
119 XCHAL_SA_REG(s,0,0,0,1, br, 4, 4, 4,0x0204, sr,4 , 16,0,0,0) \
120 XCHAL_SA_REG(s,0,0,0,1, scompare1, 4, 4, 4,0x020C, sr,12 , 32,0,0,0) \
121 XCHAL_SA_REG(s,0,0,0,1, m0, 4, 4, 4,0x0220, sr,32 , 32,0,0,0) \
122 XCHAL_SA_REG(s,0,0,0,1, m1, 4, 4, 4,0x0221, sr,33 , 32,0,0,0) \
123 XCHAL_SA_REG(s,0,0,0,1, m2, 4, 4, 4,0x0222, sr,34 , 32,0,0,0) \
124 XCHAL_SA_REG(s,0,0,0,1, m3, 4, 4, 4,0x0223, sr,35 , 32,0,0,0)
/arch/xtensa/variants/test_kc705_hifi/include/variant/
A Dtie.h117 XCHAL_SA_REG(s,1,0,0,1, acclo, 4, 4, 4,0x0210, sr,16 , 32,0,0,0) \
118 XCHAL_SA_REG(s,1,0,0,1, acchi, 4, 4, 4,0x0211, sr,17 , 8,0,0,0) \
119 XCHAL_SA_REG(s,0,0,0,1, m0, 4, 4, 4,0x0220, sr,32 , 32,0,0,0) \
120 XCHAL_SA_REG(s,0,0,0,1, m1, 4, 4, 4,0x0221, sr,33 , 32,0,0,0) \
121 XCHAL_SA_REG(s,0,0,0,1, m2, 4, 4, 4,0x0222, sr,34 , 32,0,0,0) \
122 XCHAL_SA_REG(s,0,0,0,1, m3, 4, 4, 4,0x0223, sr,35 , 32,0,0,0) \
123 XCHAL_SA_REG(s,0,0,0,1, br, 4, 4, 4,0x0204, sr,4 , 16,0,0,0) \
124 XCHAL_SA_REG(s,0,0,0,1, scompare1, 4, 4, 4,0x020C, sr,12 , 32,0,0,0)
/arch/arm64/kvm/hyp/vhe/
A DMakefile11 obj-y := timer-sr.o sysreg-sr.o debug-sr.o switch.o tlb.o
12 obj-y += ../vgic-v3-sr.o ../aarch32.o ../vgic-v2-cpuif-proxy.o ../entry.o \
/arch/mips/sgi-ip27/
A Dip27-nmi.c84 pr_emerg("Status: %08lx ", nr->sr); in nmi_cpu_eframe_save()
86 if (nr->sr & ST0_KX) in nmi_cpu_eframe_save()
88 if (nr->sr & ST0_SX) in nmi_cpu_eframe_save()
90 if (nr->sr & ST0_UX) in nmi_cpu_eframe_save()
93 switch (nr->sr & ST0_KSU) { in nmi_cpu_eframe_save()
108 if (nr->sr & ST0_ERL) in nmi_cpu_eframe_save()
110 if (nr->sr & ST0_EXL) in nmi_cpu_eframe_save()
112 if (nr->sr & ST0_IE) in nmi_cpu_eframe_save()
/arch/sh/kernel/
A Drelocate_kernel.S39 stc.l sr, @-r15
45 stc sr, r8
47 ldc r8, sr
60 stc sr, r8
62 ldc r8, sr
92 stc sr, r8
94 ldc r8, sr
106 stc sr, r8
108 ldc r8, sr
121 stc sr, r8
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/arch/powerpc/kernel/
A Dsignal_32.c467 struct mcontext __user *sr, int sig) in restore_user_regs() argument
475 if (!user_read_access_begin(sr, sizeof(*sr))) in restore_user_regs()
483 unsafe_restore_general_regs(regs, sr, failed); in restore_user_regs()
502 sizeof(sr->mc_vregs), failed); in restore_user_regs()
573 struct mcontext __user *sr, in restore_tm_user_regs() argument
588 if (!user_read_access_begin(sr, sizeof(*sr))) in restore_tm_user_regs()
602 sizeof(sr->mc_vregs), failed); in restore_tm_user_regs()
613 (u32 __user *)&sr->mc_vregs[32], failed); in restore_tm_user_regs()
645 sizeof(sr->mc_vregs), failed); in restore_tm_user_regs()
1304 struct mcontext __user *sr; in COMPAT_SYSCALL_DEFINE0() local
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/arch/csky/include/asm/
A Dptrace.h23 #define user_mode(regs) (!((regs)->sr & PS_S))
26 #define trap_no(regs) ((regs->sr >> 16) & 0xff)
42 return ((regs->sr >> 16) & 0xff) == VEC_TRAP0; in in_syscall()
47 regs->sr &= ~(0xff << 16); in forget_syscall()
/arch/xtensa/include/asm/
A Dprocessor.h230 #define xtensa_set_sr(x, sr) \ argument
232 __asm__ __volatile__ ("wsr %0, "__stringify(sr) :: \
236 #define xtensa_get_sr(sr) \ argument
239 __asm__ __volatile__ ("rsr %0, "__stringify(sr) : "=a"(v)); \
243 #define xtensa_xsr(x, sr) \ argument
246 __asm__ __volatile__ ("xsr %0, " __stringify(sr) : "+a"(__v__)); \
/arch/powerpc/platforms/44x/
A Duic.c57 u32 er, sr; in uic_unmask_irq() local
59 sr = 1 << (31-src); in uic_unmask_irq()
63 mtdcr(uic->dcrbase + UIC_SR, sr); in uic_unmask_irq()
65 er |= sr; in uic_unmask_irq()
100 u32 er, sr; in uic_mask_ack_irq() local
102 sr = 1 << (31-src); in uic_mask_ack_irq()
105 er &= ~sr; in uic_mask_ack_irq()
116 mtdcr(uic->dcrbase + UIC_SR, sr); in uic_mask_ack_irq()
/arch/csky/kernel/
A Dptrace.c42 regs->sr = (regs->sr & TRACE_MODE_MASK) | TRACE_MODE_RUN; in singlestep_disable()
45 regs->sr |= BIT(6); in singlestep_disable()
53 regs->sr = (regs->sr & TRACE_MODE_MASK) | TRACE_MODE_SI; in singlestep_enable()
56 regs->sr &= ~BIT(6); in singlestep_enable()
102 regs.sr = (regs.sr & BIT(0)) | (task_pt_regs(target)->sr & ~BIT(0)); in gpr_set()
210 REG_OFFSET_NAME(sr),
486 pr_info("PSR: 0x%08lx\n", (long)fp->sr); in show_regs()
/arch/arm64/boot/dts/broadcom/stingray/
A Dstingray-clock.dtsi33 #include <dt-bindings/clock/bcm-sr.h>
51 compatible = "brcm,sr-genpll0";
63 compatible = "brcm,sr-genpll2";
75 compatible = "brcm,sr-genpll3";
85 compatible = "brcm,sr-genpll4";
97 compatible = "brcm,sr-genpll5";
107 compatible = "brcm,sr-lcpll0";
118 compatible = "brcm,sr-lcpll1";
/arch/powerpc/include/asm/book3s/32/
A Dmmu-hash.h71 .macro uus_addi sr reg1 reg2 imm
72 .if NUM_USER_SEGMENTS > \sr
77 .macro uus_mtsr sr reg1
78 .if NUM_USER_SEGMENTS > \sr
79 mtsr \sr, \reg1
/arch/powerpc/kvm/
A Dbook3s_32_mmu_host.c305 u32 sr; in kvmppc_mmu_map_segment() local
312 svcpu->sr[esid] = SR_INVALID; in kvmppc_mmu_map_segment()
322 sr = map->host_vsid | SR_KP; in kvmppc_mmu_map_segment()
323 svcpu->sr[esid] = sr; in kvmppc_mmu_map_segment()
325 dprintk_sr("MMU: mtsr %d, 0x%x\n", esid, sr); in kvmppc_mmu_map_segment()
337 dprintk_sr("MMU: flushing all segments (%d)\n", ARRAY_SIZE(svcpu->sr)); in kvmppc_mmu_flush_segments()
338 for (i = 0; i < ARRAY_SIZE(svcpu->sr); i++) in kvmppc_mmu_flush_segments()
339 svcpu->sr[i] = SR_INVALID; in kvmppc_mmu_flush_segments()

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