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Searched refs:sr1 (Results 1 – 17 of 17) sorted by relevance

/arch/parisc/kernel/
A Dpacache.S79 mtsp %r20, %sr1
85 pitlbe %r0(%sr1, %r28)
94 mtsp %r20, %sr1
123 mtsp %r20, %sr1
129 pdtlbe %r0(%sr1, %r28)
138 mtsp %r20, %sr1
183 3: pdtlbe %r0(%sr1,%r0)
200 mtsp %r0, %sr1
216 fice,m %arg1(%sr1, %arg0)
261 mtsp %r0, %sr1
[all …]
A Dentry.S1200 mtsp spc,%sr1
1202 idtlba pte,(%sr1,va)
1234 mtsp spc,%sr1
1236 idtlba pte,(%sr1,va)
1398 mtsp spc,%sr1
1400 iitlba pte,(%sr1,va)
1422 mtsp spc,%sr1
1424 iitlba pte,(%sr1,va)
1530 mtsp spc,%sr1
1532 idtlba pte,(%sr1,va)
[all …]
A Dkgdb.c73 gr->sr1 = regs->sr[1]; in pt_regs_to_gdb_regs()
104 regs->sr[1] = gr->sr1; in gdb_regs_to_pt_regs()
A Dhead.S284 mtsp %r0,%sr1
A Dsyscall.S306 mfsp %sr1,%r2
/arch/powerpc/platforms/ps3/
A Dspu.c90 u64 sr1; member
351 spu_pdata(spu)->cache.sr1 = 0x33; in ps3_create_spu()
532 static void mfc_sr1_set(struct spu *spu, u64 sr1) in mfc_sr1_set() argument
539 BUG_ON((sr1 & allowed) != (spu_pdata(spu)->cache.sr1 & allowed)); in mfc_sr1_set()
541 spu_pdata(spu)->cache.sr1 = sr1; in mfc_sr1_set()
545 spu_pdata(spu)->cache.sr1); in mfc_sr1_set()
550 return spu_pdata(spu)->cache.sr1; in mfc_sr1_get()
/arch/powerpc/platforms/cell/spufs/
A Drun.c86 u64 sr1; in spu_setup_isolated() local
125 sr1 = spu_mfc_sr1_get(ctx->spu); in spu_setup_isolated()
126 sr1 &= ~MFC_STATE1_PROBLEM_STATE_MASK; in spu_setup_isolated()
127 spu_mfc_sr1_set(ctx->spu, sr1); in spu_setup_isolated()
169 sr1 |= MFC_STATE1_PROBLEM_STATE_MASK; in spu_setup_isolated()
170 spu_mfc_sr1_set(ctx->spu, sr1); in spu_setup_isolated()
A Dhw_ops.c228 u64 sr1; in spu_hw_master_start() local
231 sr1 = spu_mfc_sr1_get(spu) | MFC_STATE1_MASTER_RUN_CONTROL_MASK; in spu_hw_master_start()
232 spu_mfc_sr1_set(spu, sr1); in spu_hw_master_start()
239 u64 sr1; in spu_hw_master_stop() local
242 sr1 = spu_mfc_sr1_get(spu) & ~MFC_STATE1_MASTER_RUN_CONTROL_MASK; in spu_hw_master_stop()
243 spu_mfc_sr1_set(spu, sr1); in spu_hw_master_stop()
A Dbacking_ops.c298 u64 sr1; in spu_backing_master_start() local
301 sr1 = csa->priv1.mfc_sr1_RW | MFC_STATE1_MASTER_RUN_CONTROL_MASK; in spu_backing_master_start()
302 csa->priv1.mfc_sr1_RW = sr1; in spu_backing_master_start()
309 u64 sr1; in spu_backing_master_stop() local
312 sr1 = csa->priv1.mfc_sr1_RW & ~MFC_STATE1_MASTER_RUN_CONTROL_MASK; in spu_backing_master_stop()
313 csa->priv1.mfc_sr1_RW = sr1; in spu_backing_master_stop()
/arch/powerpc/include/asm/
A Dspu_priv1.h31 void (*mfc_sr1_set) (struct spu *spu, u64 sr1);
111 spu_mfc_sr1_set (struct spu *spu, u64 sr1) in spu_mfc_sr1_set() argument
113 spu_priv1_ops->mfc_sr1_set(spu, sr1); in spu_mfc_sr1_set()
/arch/parisc/include/asm/
A Dkgdb.h46 unsigned long sr1; member
A Dasmregs.h70 sr1: .reg %sr1
A Dassembly.h464 SAVE_SP (%sr1, PT_SR1 (\regs))
503 REST_SP (%sr1, PT_SR1 (\regs))
/arch/arm64/boot/dts/ti/
A Dk3-am65-iot2050-common-pg1.dtsi46 compatible = "ti,am654-sr1-icssg-prueth";
A Dk3-am654-base-board.dts475 * SD card interface might fail. Boards with sr1.0 are recommended to
/arch/arm/boot/dts/ti/omap/
A Domap34xx-omap36xx-clocks.dtsi169 sr1_fck: clock-sr1-fck@6 {
/arch/parisc/lib/
A Dlusercopy.S97 srcspc = sr1

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