| /arch/hexagon/include/asm/ |
| A D | bitops.h | 55 static inline int test_and_set_bit(int nr, volatile void *addr) in test_and_set_bit() function
113 test_and_set_bit(nr, addr); in set_bit()
139 test_and_set_bit(nr, addr); in arch___set_bit()
158 return test_and_set_bit(nr, addr); in arch___test_and_set_bit()
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| /arch/x86/kernel/cpu/ |
| A D | perfctr-watchdog.c | 117 if (!test_and_set_bit(counter, perfctr_nmi_owner)) in reserve_perfctr_nmi()
145 if (!test_and_set_bit(counter, evntsel_nmi_owner)) in reserve_evntsel_nmi()
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| /arch/sh/boards/mach-x3proto/ |
| A D | ilsel.c | 103 } while (test_and_set_bit(bit, &ilsel_level_map)); in ilsel_enable()
126 if (test_and_set_bit(bit, &ilsel_level_map)) in ilsel_enable_fixed()
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| /arch/m68k/include/asm/ |
| A D | bitops.h | 201 #define test_and_set_bit(nr, vaddr) bset_reg_test_and_set_bit(nr, vaddr) macro
203 #define test_and_set_bit(nr, vaddr) bset_mem_test_and_set_bit(nr, vaddr) macro
205 #define test_and_set_bit(nr, vaddr) (__builtin_constant_p(nr) ? \ macro
213 return test_and_set_bit(nr, addr); in arch___test_and_set_bit()
557 #define test_and_set_bit_lock test_and_set_bit
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| /arch/x86/include/asm/ |
| A D | posted_intr.h | 95 return test_and_set_bit(POSTED_INTR_ON, (unsigned long *)&pi_desc->control); in pi_test_and_set_on()
110 return test_and_set_bit(vector, pi_desc->pir); in pi_test_and_set_pir()
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| /arch/sparc/lib/ |
| A D | bitops.S | 14 ENTRY(test_and_set_bit) /* %o0=nr, %o1=addr */
33 ENDPROC(test_and_set_bit)
34 EXPORT_SYMBOL(test_and_set_bit)
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| /arch/arm64/include/asm/ |
| A D | mte.h | 85 if (!test_and_set_bit(PG_mte_lock, &page->flags)) in try_page_mte_tagging()
199 if (!test_and_set_bit(PG_mte_lock, &folio->flags)) in folio_try_hugetlb_mte_tagging()
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| A D | sync_bitops.h | 21 #define sync_test_and_set_bit(nr, p) test_and_set_bit(nr, p)
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| /arch/sparc/include/asm/ |
| A D | bitops_64.h | 19 int test_and_set_bit(unsigned long nr, volatile unsigned long *addr);
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| A D | bitops_32.h | 32 static inline int test_and_set_bit(unsigned long nr, volatile unsigned long *addr) in test_and_set_bit() function
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| /arch/arm/mm/ |
| A D | copypage-xscale.c | 90 if (!test_and_set_bit(PG_dcache_clean, &src->flags)) in xscale_mc_copy_user_highpage()
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| A D | copypage-v4mc.c | 70 if (!test_and_set_bit(PG_dcache_clean, &src->flags)) in v4_mc_copy_user_highpage()
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| A D | copypage-v6.c | 76 if (!test_and_set_bit(PG_dcache_clean, &src->flags)) in v6_copy_user_highpage_aliasing()
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| /arch/csky/abiv1/ |
| A D | cacheflush.c | 59 if (!test_and_set_bit(PG_dcache_clean, &folio->flags)) in update_mmu_cache_range()
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| /arch/arm/include/asm/ |
| A D | bitops.h | 194 #define test_and_set_bit(nr,p) ATOMIC_BITOP(test_and_set_bit,nr,p) macro
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| /arch/alpha/include/asm/ |
| A D | spinlock.h | 52 return !test_and_set_bit(0, &lock->lock); in arch_spin_trylock()
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| /arch/openrisc/include/asm/bitops/ |
| A D | atomic.h | 63 static inline int test_and_set_bit(int nr, volatile unsigned long *addr) in test_and_set_bit() function
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| /arch/sh/include/asm/ |
| A D | bitops-grb.h | 75 static inline int test_and_set_bit(int nr, volatile void * addr) in test_and_set_bit() function
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| A D | bitops-llsc.h | 68 static inline int test_and_set_bit(int nr, volatile void *addr) in test_and_set_bit() function
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| A D | bitops-cas.h | 50 static inline int test_and_set_bit(int nr, volatile void *addr) in test_and_set_bit() function
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| /arch/openrisc/mm/ |
| A D | cache.c | 86 int dirty = !test_and_set_bit(PG_dc_clean, &folio->flags); in update_cache()
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| /arch/csky/abiv2/ |
| A D | cacheflush.c | 24 if (test_and_set_bit(PG_dcache_clean, &folio->flags)) in update_mmu_cache_range()
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| /arch/microblaze/include/asm/ |
| A D | mmu_context_mm.h | 86 while (test_and_set_bit(ctx, context_map)) { in get_mmu_context()
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| /arch/powerpc/mm/book3s32/ |
| A D | mmu_context.c | 55 while (test_and_set_bit(ctx, context_map)) { in __init_new_context()
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| /arch/mips/sgi-ip27/ |
| A D | ip27-init.c | 51 if (test_and_set_bit(nasid, hub_init_mask)) in per_hub_init()
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