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/arch/loongarch/include/asm/
A Dasmmacro.h47 andi \tmp, \tmp, FPU_CSR_TM
48 beqz \tmp, 1f
50 x86mftop \tmp
133 PTR_ADD \tmp, \tmp, \thread
170 PTR_ADD \tmp, \tmp, \thread
207 PTR_ADD \tmp, \thread, \tmp
244 PTR_ADD \tmp, \thread, \tmp
380 not \tmp, zero
417 PTR_ADD \tmp, \thread, \tmp
454 PTR_ADD \tmp, \thread, \tmp
[all …]
/arch/mips/sgi-ip22/
A Dip22-mc.c64 size = get_bank_size(tmp); in probe_memory()
77 u32 tmp; in sgimc_init() local
94 tmp = sgimc->cpuctrl0; in sgimc_init()
95 tmp &= ~SGIMC_CCTRL0_WDOG; in sgimc_init()
96 sgimc->cpuctrl0 = tmp; in sgimc_init()
109 tmp = sgimc->cpuctrl0; in sgimc_init()
114 sgimc->cpuctrl0 = tmp; in sgimc_init()
119 tmp = sgimc->cpuctrl1; in sgimc_init()
120 tmp &= ~0xf; in sgimc_init()
121 tmp |= 0xd; in sgimc_init()
[all …]
/arch/csky/kernel/probes/
A Dsimulate-insn.c127 csky_insn_reg_get_val(regs, tmp, &tmp); in simulate_jmp16()
137 csky_insn_reg_get_val(regs, tmp, &tmp); in simulate_jmp32()
147 csky_insn_reg_get_val(regs, tmp, &tmp); in simulate_jsr16()
159 csky_insn_reg_get_val(regs, tmp, &tmp); in simulate_jsr32()
201 tmp += 1; in simulate_pop16()
206 tmp += 1; in simulate_pop16()
222 tmp += 1; in simulate_pop32()
227 tmp += 1; in simulate_pop32()
232 tmp += 1; in simulate_pop32()
250 csky_insn_reg_get_val(regs, tmp, &tmp); in simulate_bez32()
[all …]
/arch/arm/include/asm/
A Duaccess-asm.h21 adds \tmp, \addr, #\size - 1
22 sbcscc \tmp, \tmp, \limit
33 sub \tmp, \limit, #1
34 subs \tmp, \tmp, \addr @ tmp = limit - 1 - addr
35 addhs \tmp, \tmp, #1 @ if (tmp >= 0) {
36 subshs \tmp, \tmp, \size @ tmp = limit - (addr + size) }
62 mcr p15, 0, \tmp, c3, c0, 0
77 orr \tmp, \tmp, #TTBCR_EPD0 | TTBCR_T0SZ_MASK
78 orr \tmp, \tmp, #TTBCR_A1
91 bic \tmp, \tmp, #TTBCR_EPD0 | TTBCR_T0SZ_MASK
[all …]
A Dvfpmacros.h20 .macro VFPFLDMIA, base, tmp
30 ldr \tmp, =elf_hwcap @ may not have MVFR regs
31 ldr \tmp, [\tmp, #0]
32 tst \tmp, #HWCAP_VFPD32
37 and \tmp, \tmp, #MVFR0_A_SIMD_MASK @ A_SIMD field
38 cmp \tmp, #2 @ 32 x 64bit registers?
46 .macro VFPFSTMIA, base, tmp
56 ldr \tmp, [\tmp, #0]
57 tst \tmp, #HWCAP_VFPD32
62 and \tmp, \tmp, #MVFR0_A_SIMD_MASK @ A_SIMD field
[all …]
/arch/powerpc/crypto/
A Daesp10-ppc.pl211 vsldoi $tmp,$zero,$tmp,12 # >>32
213 vsldoi $tmp,$zero,$tmp,12 # >>32
231 vsldoi $tmp,$zero,$tmp,12 # >>32
233 vsldoi $tmp,$zero,$tmp,12 # >>32
248 vsldoi $tmp,$zero,$tmp,12 # >>32
250 vsldoi $tmp,$zero,$tmp,12 # >>32
284 vsldoi $tmp,$zero,$tmp,12 # >>32
286 vsldoi $tmp,$zero,$tmp,12 # >>32
291 vxor $tmp,$tmp,$in1
310 vsldoi $tmp,$zero,$tmp,12 # >>32
[all …]
/arch/sh/include/asm/
A Dspinlock-llsc.h28 unsigned long tmp; in arch_spin_lock() local
48 unsigned long tmp; in arch_spin_unlock() local
55 : "=&z" (tmp) in arch_spin_unlock()
63 unsigned long tmp, oldval; in arch_spin_trylock() local
92 unsigned long tmp; in arch_read_lock() local
102 : "=&z" (tmp) in arch_read_lock()
110 unsigned long tmp; in arch_read_unlock() local
118 : "=&z" (tmp) in arch_read_unlock()
126 unsigned long tmp; in arch_write_lock() local
136 : "=&z" (tmp) in arch_write_lock()
[all …]
A Dbitops-grb.h9 unsigned long tmp; in set_bit() local
23 : "=&r" (tmp), in set_bit()
33 unsigned long tmp; in clear_bit() local
46 : "=&r" (tmp), in clear_bit()
56 unsigned long tmp; in change_bit() local
69 : "=&r" (tmp), in change_bit()
79 unsigned long tmp; in test_and_set_bit() local
97 : "=&r" (tmp), in test_and_set_bit()
110 unsigned long tmp; in test_and_clear_bit() local
130 : "=&r" (tmp), in test_and_clear_bit()
[all …]
A Dbitops-llsc.h9 unsigned long tmp; in set_bit() local
20 : "=&z" (tmp) in set_bit()
30 unsigned long tmp; in clear_bit() local
41 : "=&z" (tmp) in clear_bit()
51 unsigned long tmp; in change_bit() local
62 : "=&z" (tmp) in change_bit()
72 unsigned long tmp; in test_and_set_bit() local
85 : "=&z" (tmp), "=&r" (retval) in test_and_set_bit()
97 unsigned long tmp; in test_and_clear_bit() local
111 : "=&z" (tmp), "=&r" (retval) in test_and_clear_bit()
[all …]
/arch/arm/mm/
A Dabort-macro.S13 .macro do_thumb_abort, fsr, pc, psr, tmp
16 ldrh \tmp, [\pc] @ Read aborted Thumb instruction
18 and \tmp, \tmp, # 0xfe00 @ Mask opcode field
19 cmp \tmp, # 0x5600 @ Is it ldrsb?
20 orreq \tmp, \tmp, #1 << 11 @ Set L-bit if yes
21 tst \tmp, #1 << 11 @ L = 0 -> write
34 .macro teq_ldrd, tmp, insn
35 mov \tmp, #0x0e100000
36 orr \tmp, #0x000000f0
37 and \tmp, \insn, \tmp
[all …]
/arch/xtensa/include/asm/
A Dtlbflush.h66 unsigned long tmp; in itlb_probe() local
68 return tmp; in itlb_probe()
73 unsigned long tmp; in dtlb_probe() local
75 return tmp; in dtlb_probe()
125 unsigned long tmp; in read_ptevaddr_register() local
127 return tmp; in read_ptevaddr_register()
178 unsigned long tmp; in read_dtlb_virtual() local
180 return tmp; in read_dtlb_virtual()
187 return tmp; in read_dtlb_translation()
194 return tmp; in read_itlb_virtual()
[all …]
A Datomic.h61 unsigned long tmp; \
70 : [result] "=&a" (result), [tmp] "=&a" (tmp) \
79 unsigned long tmp; \
89 : [result] "=&a" (result), [tmp] "=&a" (tmp) \
100 unsigned long tmp; \
109 : [result] "=&a" (result), [tmp] "=&a" (tmp) \
114 return tmp; \
130 : [result] "=&a" (result), [tmp] "=&a" (tmp), \
150 : [result] "=&a" (result), [tmp] "=&a" (tmp), \
171 : [result] "=&a" (result), [tmp] "=&a" (tmp), \
[all …]
/arch/mips/include/asm/octeon/
A Dcvmx-spinlock.h105 unsigned int tmp; in cvmx_spinlock_trylock() local
117 [val] "+m"(lock->value), [tmp] "=&r"(tmp) in cvmx_spinlock_trylock()
120 return tmp != 0; /* normalize to 0 or 1 */ in cvmx_spinlock_trylock()
130 unsigned int tmp; in cvmx_spinlock_lock() local
140 [val] "+m"(lock->value), [tmp] "=&r"(tmp) in cvmx_spinlock_lock()
163 unsigned int tmp; in cvmx_spinlock_bit_lock() local
177 [val] "+m"(*word), [tmp] "=&r"(tmp), [sav] "=&r"(sav) in cvmx_spinlock_bit_lock()
195 unsigned int tmp; in cvmx_spinlock_bit_trylock() local
210 [val] "+m"(*word), [tmp] "=&r"(tmp) in cvmx_spinlock_bit_trylock()
213 return tmp != 0; /* normalize to 0 or 1 */ in cvmx_spinlock_bit_trylock()
/arch/alpha/lib/
A Dudiv-qrnnd.S42 #define tmp $3 macro
55 bis n1,tmp,n1
58 subq n1,d,tmp
63 bis n1,tmp,n1
66 subq n1,d,tmp
71 bis n1,tmp,n1
74 subq n1,d,tmp
79 bis n1,tmp,n1
82 subq n1,d,tmp
96 or tmp,n0,n0
[all …]
/arch/s390/lib/
A Dfind.c21 unsigned long tmp; in find_first_bit_inv() local
24 if ((tmp = *(p++))) in find_first_bit_inv()
32 if (!tmp) /* Are any bits set? */ in find_first_bit_inv()
44 unsigned long tmp; in find_next_bit_inv() local
51 tmp = *(p++); in find_next_bit_inv()
52 tmp &= (~0UL >> offset); in find_next_bit_inv()
55 if (tmp) in find_next_bit_inv()
61 if ((tmp = *(p++))) in find_next_bit_inv()
68 tmp = *p; in find_next_bit_inv()
70 tmp &= (~0UL << (BITS_PER_LONG - size)); in find_next_bit_inv()
[all …]
/arch/mips/bcm63xx/
A Dcpu.c129 unsigned int tmp, mips_pll_fcvo; in detect_cpu_clock() local
164 unsigned int tmp, n1, n2, m1; in detect_cpu_clock() local
167 tmp = bcm_perf_readl(PERF_MIPSPLLCTL_REG); in detect_cpu_clock()
179 unsigned int tmp, n1, n2, m1; in detect_cpu_clock() local
182 tmp = bcm_ddr_readl(DDR_DMIPSPLLCFG_REG); in detect_cpu_clock()
191 unsigned int tmp, mips_pll_fcvo; in detect_cpu_clock() local
227 unsigned int tmp, p1, p2, ndiv, m1; in detect_cpu_clock() local
232 p1 = (tmp & DMIPSPLLCFG_6368_P1_MASK) >> in detect_cpu_clock()
235 p2 = (tmp & DMIPSPLLCFG_6368_P2_MASK) >> in detect_cpu_clock()
296 unsigned int tmp; in bcm63xx_cpu_init() local
[all …]
/arch/arm64/include/asm/
A Dassembler.h61 bic \tmp, \tmp, #MDSCR_EL1_SS
71 orr \tmp, \tmp, #MDSCR_EL1_SS
188 .ifb \tmp
288 ubfm \tmp, \tmp, #16, #19 // cache line size encoding
297 read_ctr \tmp
298 ubfm \tmp, \tmp, #16, #19 // cache line size encoding
309 and \tmp, \tmp, #0xf // cache line size encoding
319 and \tmp, \tmp, #0xf // cache line size encoding
592 and \tmp, \tmp, #TCR_T1SZ_MASK
751 ldr \tmp, [\tmp, #TSK_TI_PREEMPT]
[all …]
/arch/m68k/include/asm/
A Draw_io.h113 unsigned int tmp; in raw_outsb() local
121 "1" (tmp)); in raw_outsb()
146 "1" (tmp)); in raw_outsb()
160 "1" (tmp)); in raw_insw()
185 "1" (tmp)); in raw_insw()
200 "1" (tmp)); in raw_outsw()
225 "1" (tmp)); in raw_outsw()
239 "1" (tmp)); in raw_insl()
264 "1" (tmp)); in raw_insl()
279 "1" (tmp)); in raw_outsl()
[all …]
/arch/csky/include/asm/
A Duaccess.h67 int tmp; \
85 "=r"(tmp), "=r"(errcode) \
94 u32 tmp; in __put_user_fn() local
98 tmp = *(u8 *)x; in __put_user_fn()
102 tmp = *(u16 *)x; in __put_user_fn()
106 tmp = *(u32 *)x; in __put_user_fn()
144 int tmp; \
171 u32 tmp; in __get_user_fn() local
176 *(u8 *)x = (u8)tmp; in __get_user_fn()
180 *(u16 *)x = (u16)tmp; in __get_user_fn()
[all …]
/arch/sparc/include/asm/
A Dbackoff.h55 #define BACKOFF_SPIN(reg, tmp, label) \ argument
56 mov reg, tmp; \
62 sllx tmp, 7, tmp; \
63 wr tmp, 0, %asr27; \
64 clr tmp; \
66 brnz,pt tmp, 88b; \
67 sub tmp, 1, tmp; \
68 set BACKOFF_LIMIT, tmp; \
69 cmp reg, tmp; \
82 #define BACKOFF_SPIN(reg, tmp, label) argument
/arch/powerpc/platforms/pseries/
A Dreconfig.c117 char *tmp; in parse_next_property() local
122 if (!tmp) { in parse_next_property()
137 *length = simple_strtoul(tmp, &tmp, 10); in parse_next_property()
143 if (*tmp != ' ' || ++tmp >= end) { in parse_next_property()
157 else if (tmp < end && *tmp != ' ' && *tmp != '\0') { in parse_next_property()
162 tmp++; in parse_next_property()
300 char *tmp; in do_remove_property() local
307 if (tmp) in do_remove_property()
379 tmp++; in ofdt_write()
382 rv = do_add_node(tmp, count - (tmp - kbuf)); in ofdt_write()
[all …]
/arch/arm64/lib/
A Dstrcmp.S35 #define tmp x6 macro
59 and tmp, src1, 7
71 rev tmp, data1
73 orr tmp, tmp, REP8_7f
76 orr tmp, data1, REP8_7f
115 mov tmp, -1
116 LS_FW tmp, tmp, shift
117 orr data1, data1, tmp
118 orr data2, data2, tmp
142 orr data3, data3, tmp
[all …]
/arch/arm/mach-exynos/
A Dpm.c52 unsigned long tmp; in exynos_cpu_save_register() local
56 : "=r" (tmp) : : "cc"); in exynos_cpu_save_register()
58 save_arm_register[0] = tmp; in exynos_cpu_save_register()
64 save_arm_register[1] = tmp; in exynos_cpu_save_register()
69 unsigned long tmp; in exynos_cpu_restore_register() local
72 tmp = save_arm_register[0]; in exynos_cpu_restore_register()
75 : : "r" (tmp) in exynos_cpu_restore_register()
79 tmp = save_arm_register[1]; in exynos_cpu_restore_register()
82 : : "r" (tmp) in exynos_cpu_restore_register()
88 unsigned long tmp; in exynos_pm_central_suspend() local
[all …]
/arch/openrisc/include/asm/bitops/
A Datomic.h16 unsigned long tmp; in set_bit() local
24 : "=&r"(tmp) in set_bit()
33 unsigned long tmp; in clear_bit() local
41 : "=&r"(tmp) in clear_bit()
50 unsigned long tmp; in change_bit() local
58 : "=&r"(tmp) in change_bit()
68 unsigned long tmp; in test_and_set_bit() local
76 : "=&r"(old), "=&r"(tmp) in test_and_set_bit()
88 unsigned long tmp; in test_and_clear_bit() local
96 : "=&r"(old), "=&r"(tmp) in test_and_clear_bit()
[all …]
/arch/m68k/mm/
A Dmemory.c102 int tmp; in cache_clear() local
109 if ((tmp = -paddr & (PAGE_SIZE - 1))) { in cache_clear()
111 if ((len -= tmp) <= 0) in cache_clear()
113 paddr += tmp; in cache_clear()
115 tmp = PAGE_SIZE; in cache_clear()
117 while ((len -= tmp) >= 0) { in cache_clear()
119 paddr += tmp; in cache_clear()
121 if ((len += tmp)) in cache_clear()
151 int tmp = PAGE_SIZE; in cache_push() local
168 paddr += tmp; in cache_push()
[all …]

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