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Searched refs:write_sysreg_el1 (Results 1 – 14 of 14) sorted by relevance

/arch/arm64/kvm/hyp/vhe/
A Dsysreg-sr.c95 write_sysreg_el1(__vcpu_sys_reg(vcpu, MAIR_EL2), SYS_MAIR); in __sysreg_restore_vel2_state()
96 write_sysreg_el1(__vcpu_sys_reg(vcpu, VBAR_EL2), SYS_VBAR); in __sysreg_restore_vel2_state()
117 write_sysreg_el1(val, SYS_SCTLR); in __sysreg_restore_vel2_state()
119 write_sysreg_el1(val, SYS_CPACR); in __sysreg_restore_vel2_state()
121 write_sysreg_el1(val, SYS_TTBR0); in __sysreg_restore_vel2_state()
123 write_sysreg_el1(val, SYS_TCR); in __sysreg_restore_vel2_state()
130 write_sysreg_el1(__vcpu_sys_reg(vcpu, PIR_EL2), SYS_PIR); in __sysreg_restore_vel2_state()
135 write_sysreg_el1(__vcpu_sys_reg(vcpu, POR_EL2), SYS_POR); in __sysreg_restore_vel2_state()
138 write_sysreg_el1(__vcpu_sys_reg(vcpu, ESR_EL2), SYS_ESR); in __sysreg_restore_vel2_state()
141 write_sysreg_el1(__vcpu_sys_reg(vcpu, FAR_EL2), SYS_FAR); in __sysreg_restore_vel2_state()
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A Dtlb.c45 write_sysreg_el1(val, SYS_TCR); in enter_vmid_context()
48 write_sysreg_el1(val, SYS_SCTLR); in enter_vmid_context()
85 write_sysreg_el1(cxt->tcr, SYS_TCR); in exit_vmid_context()
86 write_sysreg_el1(cxt->sctlr, SYS_SCTLR); in exit_vmid_context()
/arch/arm64/kvm/hyp/include/hyp/
A Dsysreg-sr.h220 write_sysreg_el1(ctxt_sys_reg(ctxt, TCR_EL1), SYS_TCR); in __sysreg_restore_el1_state()
227 write_sysreg_el1((ctxt_sys_reg(ctxt, TCR_EL1) | in __sysreg_restore_el1_state()
240 write_sysreg_el1(ctxt_sys_reg(ctxt, PIR_EL1), SYS_PIR); in __sysreg_restore_el1_state()
245 write_sysreg_el1(ctxt_sys_reg(ctxt, POR_EL1), SYS_POR); in __sysreg_restore_el1_state()
247 write_sysreg_el1(ctxt_sys_reg(ctxt, ESR_EL1), SYS_ESR); in __sysreg_restore_el1_state()
250 write_sysreg_el1(ctxt_sys_reg(ctxt, FAR_EL1), SYS_FAR); in __sysreg_restore_el1_state()
251 write_sysreg_el1(ctxt_sys_reg(ctxt, MAIR_EL1), SYS_MAIR); in __sysreg_restore_el1_state()
252 write_sysreg_el1(ctxt_sys_reg(ctxt, VBAR_EL1), SYS_VBAR); in __sysreg_restore_el1_state()
279 write_sysreg_el1(ctxt_sys_reg(ctxt, TCR_EL1), SYS_TCR); in __sysreg_restore_el1_state()
283 write_sysreg_el1(ctxt_sys_reg(ctxt, ELR_EL1), SYS_ELR); in __sysreg_restore_el1_state()
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A Dswitch.h751 write_sysreg_el1(val, SYS_SCTLR); in handle_tx2_tvm()
754 write_sysreg_el1(val, SYS_TTBR0); in handle_tx2_tvm()
757 write_sysreg_el1(val, SYS_TTBR1); in handle_tx2_tvm()
760 write_sysreg_el1(val, SYS_TCR); in handle_tx2_tvm()
763 write_sysreg_el1(val, SYS_ESR); in handle_tx2_tvm()
766 write_sysreg_el1(val, SYS_FAR); in handle_tx2_tvm()
769 write_sysreg_el1(val, SYS_AFSR0); in handle_tx2_tvm()
772 write_sysreg_el1(val, SYS_AFSR1); in handle_tx2_tvm()
775 write_sysreg_el1(val, SYS_MAIR); in handle_tx2_tvm()
778 write_sysreg_el1(val, SYS_AMAIR); in handle_tx2_tvm()
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/arch/arm64/kvm/hyp/nvhe/
A Ddebug-sr.c35 write_sysreg_el1(0, SYS_PMSCR); in __debug_save_spe()
51 write_sysreg_el1(pmscr_el1, SYS_PMSCR); in __debug_restore_spe()
57 write_sysreg_el1(new_trfcr, SYS_TRFCR); in __trace_do_switch()
109 write_sysreg_el1(0, SYS_BRBCR); in __debug_save_brbe()
118 write_sysreg_el1(brbcr_el1, SYS_BRBCR); in __debug_restore_brbe()
A Dtlb.c88 write_sysreg_el1(val, SYS_TCR); in enter_vmid_context()
95 write_sysreg_el1(val, SYS_SCTLR); in enter_vmid_context()
140 write_sysreg_el1(cxt->sctlr, SYS_SCTLR); in exit_vmid_context()
144 write_sysreg_el1(cxt->tcr, SYS_TCR); in exit_vmid_context()
A Dswitch.c67 write_sysreg_el1(ctxt_sys_reg(ctxt, SCTLR_EL1), SYS_SCTLR); in __activate_traps()
69 write_sysreg_el1(ctxt_sys_reg(ctxt, TCR_EL1), SYS_TCR); in __activate_traps()
89 write_sysreg_el1(val | TCR_EPD1_MASK | TCR_EPD0_MASK, SYS_TCR); in __deactivate_traps()
92 write_sysreg_el1(val | SCTLR_ELx_M, SYS_SCTLR); in __deactivate_traps()
A Dsys_regs.c261 write_sysreg_el1(esr, SYS_ESR); in inject_undef64()
262 write_sysreg_el1(read_sysreg_el2(SYS_ELR), SYS_ELR); in inject_undef64()
A Dpsci-relay.c221 write_sysreg_el1(INIT_SCTLR_EL1_MMU_OFF, SYS_SCTLR); in __kvm_host_psci_cpu_entry()
A Dhyp-main.c57 write_sysreg_el1(sve_state->zcr_el1, SYS_ZCR); in __hyp_sve_restore_host()
/arch/arm64/kvm/
A Dat.c499 write_sysreg_el1(config->ttbr0, SYS_TTBR0); in __mmu_config_restore()
500 write_sysreg_el1(config->ttbr1, SYS_TTBR1); in __mmu_config_restore()
501 write_sysreg_el1(config->tcr, SYS_TCR); in __mmu_config_restore()
502 write_sysreg_el1(config->mair, SYS_MAIR); in __mmu_config_restore()
504 write_sysreg_el1(config->tcr2, SYS_TCR2); in __mmu_config_restore()
506 write_sysreg_el1(config->pir, SYS_PIR); in __mmu_config_restore()
507 write_sysreg_el1(config->pire0, SYS_PIRE0); in __mmu_config_restore()
510 write_sysreg_el1(config->por_el1, SYS_POR); in __mmu_config_restore()
514 write_sysreg_el1(config->sctlr, SYS_SCTLR); in __mmu_config_restore()
1238 write_sysreg_el1(vcpu_read_sys_reg(vcpu, TCR_EL1), SYS_TCR); in __kvm_at_s1e01_fast()
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A Dsys_regs.c242 write_sysreg_el1(val, SYS_CNTKCTL); in vcpu_write_sys_reg()
/arch/arm64/include/asm/
A Dkvm_hyp.h30 #define write_sysreg_el1(v,r) write_sysreg_s(v, r##_EL12) macro
64 #define write_sysreg_el1(v,r) write_sysreg_elx(v, r, _EL1, _EL12) macro
/arch/arm64/kvm/hyp/
A Dexception.c54 write_sysreg_el1(val, SYS_SPSR); in __vcpu_write_spsr()

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