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Searched refs:writew (Results 1 – 25 of 35) sorted by relevance

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/arch/m68k/coldfire/
A Dnettel.c109 writew(1, NETTEL_SMC0_ADDR + SMC91xx_BANKSELECT); in nettel_smc91x_setmac()
110 writew(macp[0], ioaddr + SMC91xx_BASEMAC); in nettel_smc91x_setmac()
111 writew(macp[1], ioaddr + SMC91xx_BASEMAC + 2); in nettel_smc91x_setmac()
112 writew(macp[2], ioaddr + SMC91xx_BASEMAC + 4); in nettel_smc91x_setmac()
125 writew(0x00ec, MCFSIM_PADDR); in nettel_smc91x_init()
127 writew(1, NETTEL_SMC0_ADDR + SMC91xx_BANKSELECT); in nettel_smc91x_init()
128 writew(0x0067, NETTEL_SMC0_ADDR + SMC91xx_BASEADDR); in nettel_smc91x_init()
132 writew(0x1180, MCFSIM_CSCR3); in nettel_smc91x_init()
A Dm527x.c61 writew(par, MCFGPIO_PAR_TIMER); in m527x_qspi_init()
64 writew(0x003e, MCFGPIO_PAR_QSPI); in m527x_qspi_init()
89 writew(par, MCFGPIO_PAR_FECI2C); in m527x_i2c_init()
105 writew(sepmask, MCFGPIO_PAR_UART); in m527x_uarts_init()
122 writew(par | 0xf00, MCFGPIO_PAR_FECI2C); in m527x_fec_init()
128 writew(par | 0xa0, MCFGPIO_PAR_FECI2C); in m527x_fec_init()
A Dm528x.c69 writew(paspar, MCFGPIO_PASPAR); in m528x_i2c_init()
93 writew(v16 | 0xf00, MCFGPIO_PASPAR); in m528x_fec_init()
113 writew(readw(MCFGPIO_PEPAR) & ~(1 << (5 * 2)), MCFGPIO_PEPAR); in wildfiremod_halt()
A Dm53xx.c169 writew(0x01f0, MCFGPIO_PAR_QSPI); in m53xx_qspi_init()
191 writew(readw(MCFGPIO_PAR_UART) | 0x0FFF, MCFGPIO_PAR_UART); in m53xx_uarts_init()
308 writew(0, MCF_WTM_WCR); in wtm_init()
344 writew(0xffff, 0x10080000); in fbcs_init()
458 writew(MCF_GPIO_PAR_UART_PAR_URXD0 | MCF_GPIO_PAR_UART_PAR_UTXD0, in gpio_init()
560 writew(MCF_CCM_CDR_LPDIV(div) | MCF_CCM_CDR_SSIDIV(temp), MCF_CCM_CDR); in clock_limp()
562 writew(readw(MCF_CCM_MISCCR) | MCF_CCM_MISCCR_LIMP, MCF_CCM_MISCCR); in clock_limp()
572 writew(readw(MCF_CCM_MISCCR) & ~MCF_CCM_MISCCR_LIMP, MCF_CCM_MISCCR); in clock_exit_limp()
A Dm520x.c132 writew(par, MCF_GPIO_PAR_UART); in m520x_qspi_init()
162 writew(par, MCF_GPIO_PAR_UART); in m520x_uarts_init()
A Dm523x.c58 writew(par, MCFGPIO_PAR_TIMER); in m523x_qspi_init()
/arch/arm/mach-spear/
A Dtime.c75 writew(CTRL_PRESCALER256, gpt_base + CR(CLKSRC)); in spear_clocksource_init()
81 writew(0xFFFF, gpt_base + LOAD(CLKSRC)); in spear_clocksource_init()
86 writew(val, gpt_base + CR(CLKSRC)); in spear_clocksource_init()
99 writew(val, gpt_base + CR(CLKEVT)); in spear_timer_shutdown()
118 writew(val, gpt_base + CR(CLKEVT)); in spear_set_oneshot()
133 writew(period, gpt_base + LOAD(CLKEVT)); in spear_set_periodic()
138 writew(val, gpt_base + CR(CLKEVT)); in spear_set_periodic()
162 writew(cycles, gpt_base + LOAD(CLKEVT)); in clockevent_next_event()
165 writew(val, gpt_base + CR(CLKEVT)); in clockevent_next_event()
174 writew(INT_STATUS, gpt_base + IR(CLKEVT)); in spear_timer_interrupt()
[all …]
/arch/m68k/include/asm/
A Dio_no.h81 #define writew writew macro
82 static inline void writew(u16 value, volatile void __iomem *addr) in writew() function
105 #define writew __raw_writew macro
A Dvga.h27 #undef writew
34 #define writew __raw_writew macro
A Dnettel.h95 writew((readw(MCFSIM_PBDAT) & ~mask) | bits, MCFSIM_PBDAT); in mcf_setppdata()
A Damigayle.h67 #define gayle_outw(v,a) writew( v, GAYLE_IO+(a) )
A Dio_mm.h335 #define writew isa_writew macro
369 #define writew(val, addr) out_le16((addr), (val)) macro
397 #define writew_relaxed(b, addr) writew(b, addr)
/arch/arm/mach-mstar/
A Dmstarv7.c94 writew(bootaddr & 0xffff, smpctrl + MSTARV7_CPU1_BOOT_ADDR_LOW); in mstarv7_boot_secondary()
95 writew((bootaddr >> 16) & 0xffff, smpctrl + MSTARV7_CPU1_BOOT_ADDR_HIGH); in mstarv7_boot_secondary()
98 writew(MSTARV7_CPU1_UNLOCK_MAGIC, smpctrl + MSTARV7_CPU1_UNLOCK); in mstarv7_boot_secondary()
/arch/csky/include/asm/
A Dio.h26 #define writew(v,c) ({ wmb(); writew_relaxed((v),(c)); }) macro
30 #define writew(v,c) ({ wmb(); writew_relaxed((v),(c)); mb(); }) macro
/arch/sparc/include/asm/
A Dio_64.h166 #define writew writew macro
167 #define writew_relaxed writew
168 static inline void writew(u16 w, volatile void __iomem *addr) in writew() function
223 writew(w, (volatile void __iomem *)addr); in outw()
445 #define iowrite16 writew
/arch/alpha/include/asm/
A Dio.h160 REMAP2(u16, writew, volatile) in REMAP1()
246 extern void writew(u16 b, volatile void __iomem *addr);
254 #define writew writew macro
455 IO_CONCAT(__IO_PREFIX,writew)(b, addr); in __raw_writew()
482 extern inline void writew(u16 b, volatile void __iomem *addr) in writew() function
593 #define writew_relaxed writew
A Dio_trivial.h80 IO_CONCAT(__IO_PREFIX,writew)(u16 b, volatile void __iomem *a) in IO_CONCAT() argument
107 IO_CONCAT(__IO_PREFIX,writew)(u16 b, volatile void __iomem *a) in IO_CONCAT() argument
/arch/nios2/include/asm/
A Dio.h25 #define writew_relaxed(x, addr) writew(x, addr)
/arch/x86/include/asm/
A Dio.h66 build_mmio_write(writew, "w", unsigned short, "r", :"memory")
84 #define writew writew macro
/arch/x86/kernel/
A Dearly_printk.c41 writew(readw(VGABASE+2*(max_xpos*k+i)), in early_vga_write()
46 writew(0x720, VGABASE + 2*(max_xpos*j + i)); in early_vga_write()
61 writew(((0x7 << 8) | (unsigned short) c), in early_vga_write()
/arch/nios2/boot/compressed/
A Dconsole.c91 writew(baudclk, uartbase + ALTERA_UART_DIVISOR_REG); in console_init()
/arch/arm/plat-orion/
A Dpcie.c198 writew(cmd, base + PCIE_CMD_OFF); in orion_pcie_setup()
280 writew(val, base + PCIE_CONF_DATA_OFF + (where & 3)); in orion_pcie_wr_conf()
/arch/arm/mach-vt8500/
A Dvt8500.c57 writew(5, pmc_base + VT8500_HCR_REG); in vt8500_power_off()
/arch/powerpc/include/asm/
A Dio.h464 #define __do_outw(val, port) writew(val,_IO_PORT(port));
533 static inline void writew(u16 val, volatile void __iomem *addr) in writew() function
537 #define writew writew macro
699 #define writew_relaxed(v, addr) writew(v, addr)
/arch/alpha/kernel/
A Dio.c150 IO_CONCAT(__IO_PREFIX,writew)(b, addr); in __raw_writew()
214 void writew(u16 b, volatile void __iomem *addr) in writew() function
237 EXPORT_SYMBOL(writew);

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