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Searched refs:ADDR_SURF_BANK_WIDTH_1 (Results 1 – 25 of 31) sorted by relevance

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/drivers/gpu/drm/amd/amdgpu/
A Dgfx_v6_0.c426 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
434 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
442 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
449 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
461 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
469 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
477 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
489 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
497 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
505 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v6_0_tiling_mode_table_init()
[all …]
A Dgfx_v8_0.c2193 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
2197 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
2201 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
2205 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
2373 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
2377 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
2381 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
2385 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
2389 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
2393 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
[all …]
A Dgfx_v7_0.c1128 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v7_0_tiling_mode_table_init()
1132 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v7_0_tiling_mode_table_init()
1136 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v7_0_tiling_mode_table_init()
1140 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v7_0_tiling_mode_table_init()
1144 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v7_0_tiling_mode_table_init()
1148 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v7_0_tiling_mode_table_init()
1152 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v7_0_tiling_mode_table_init()
1311 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v7_0_tiling_mode_table_init()
1315 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v7_0_tiling_mode_table_init()
1319 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v7_0_tiling_mode_table_init()
[all …]
/drivers/gpu/drm/radeon/
A Dsi.c2501 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in si_tiling_mode_table_init()
2510 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in si_tiling_mode_table_init()
2519 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in si_tiling_mode_table_init()
2528 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in si_tiling_mode_table_init()
2537 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in si_tiling_mode_table_init()
2546 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in si_tiling_mode_table_init()
2555 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in si_tiling_mode_table_init()
2564 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in si_tiling_mode_table_init()
2573 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in si_tiling_mode_table_init()
2582 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in si_tiling_mode_table_init()
[all …]
A Dcik.c2436 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
2440 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
2444 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
2448 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
2452 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
2456 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
2460 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
2464 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
2468 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
2579 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
[all …]
A Dsid.h1207 # define ADDR_SURF_BANK_WIDTH_1 0 macro
A Dcikd.h1261 # define ADDR_SURF_BANK_WIDTH_1 0 macro
A Devergreend.h2218 # define ADDR_SURF_BANK_WIDTH_1 0 macro
/drivers/gpu/drm/amd/include/asic_reg/bif/
A Dbif_5_1_enum.h958 ADDR_SURF_BANK_WIDTH_1 = 0x0, enumerator
A Dbif_5_0_enum.h1088 ADDR_SURF_BANK_WIDTH_1 = 0x0, enumerator
/drivers/gpu/drm/amd/include/asic_reg/smu/
A Dsmu_8_0_enum.h958 ADDR_SURF_BANK_WIDTH_1 = 0x0, enumerator
A Dsmu_7_1_0_enum.h1117 ADDR_SURF_BANK_WIDTH_1 = 0x0, enumerator
A Dsmu_7_1_1_enum.h1118 ADDR_SURF_BANK_WIDTH_1 = 0x0, enumerator
A Dsmu_7_1_2_enum.h1136 ADDR_SURF_BANK_WIDTH_1 = 0x0, enumerator
A Dsmu_7_1_3_enum.h1172 ADDR_SURF_BANK_WIDTH_1 = 0x0, enumerator
/drivers/gpu/drm/amd/include/asic_reg/gmc/
A Dgmc_8_2_enum.h958 ADDR_SURF_BANK_WIDTH_1 = 0x0, enumerator
A Dgmc_8_1_enum.h1088 ADDR_SURF_BANK_WIDTH_1 = 0x0, enumerator
/drivers/gpu/drm/amd/include/asic_reg/dce/
A Ddce_8_0_enum.h1043 ADDR_SURF_BANK_WIDTH_1 = 0x0, enumerator
A Ddce_10_0_enum.h1663 ADDR_SURF_BANK_WIDTH_1 = 0x0, enumerator
A Ddce_11_0_enum.h5530 ADDR_SURF_BANK_WIDTH_1 = 0x0, enumerator
/drivers/gpu/drm/amd/include/asic_reg/uvd/
A Duvd_6_0_enum.h971 ADDR_SURF_BANK_WIDTH_1 = 0x0, enumerator
A Duvd_5_0_enum.h1101 ADDR_SURF_BANK_WIDTH_1 = 0x0, enumerator
/drivers/gpu/drm/amd/include/asic_reg/oss/
A Doss_2_4_enum.h1253 ADDR_SURF_BANK_WIDTH_1 = 0x0, enumerator
A Doss_3_0_1_enum.h1354 ADDR_SURF_BANK_WIDTH_1 = 0x0, enumerator
A Doss_3_0_enum.h1387 ADDR_SURF_BANK_WIDTH_1 = 0x0, enumerator

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