Searched refs:AMDGPU_IRQ_STATE_ENABLE (Results 1 – 25 of 48) sorted by relevance
12
695 bool st = (state == AMDGPU_IRQ_STATE_ENABLE); in amdgpu_dm_set_hpd_irq_state()726 st = (state == AMDGPU_IRQ_STATE_ENABLE); in dm_irq_state()783 bool st = (state == AMDGPU_IRQ_STATE_ENABLE); in amdgpu_dm_set_dmub_outbox_irq_state()809 bool st = (state == AMDGPU_IRQ_STATE_ENABLE); in amdgpu_dm_set_dmub_trace_irq_state()
246 (state == AMDGPU_IRQ_STATE_ENABLE) ? 1 : 0); in xgpu_ai_set_mailbox_ack_irq()316 (state == AMDGPU_IRQ_STATE_ENABLE) ? 1 : 0); in xgpu_ai_set_mailbox_rcv_irq()
43 AMDGPU_IRQ_STATE_ENABLE, enumerator
507 (state == AMDGPU_IRQ_STATE_ENABLE) ? 1 : 0); in xgpu_vi_set_mailbox_ack_irq()540 (state == AMDGPU_IRQ_STATE_ENABLE) ? 1 : 0); in xgpu_vi_set_mailbox_rcv_irq()
306 if (state == AMDGPU_IRQ_STATE_ENABLE) in xgpu_nv_set_mailbox_ack_irq()382 if (state == AMDGPU_IRQ_STATE_ENABLE) in xgpu_nv_set_mailbox_rcv_irq()
464 if (state == AMDGPU_IRQ_STATE_ENABLE) { in nbio_v7_4_set_ras_controller_irq_state()509 if (state == AMDGPU_IRQ_STATE_ENABLE) { in nbio_v7_4_set_ras_err_event_athub_irq_state()
606 case AMDGPU_IRQ_STATE_ENABLE: in si_dma_set_trap_irq_state()622 case AMDGPU_IRQ_STATE_ENABLE: in si_dma_set_trap_irq_state()
4733 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v12_0_set_gfx_eop_interrupt_state()4784 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v12_0_set_compute_eop_interrupt_state()4890 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v12_0_set_priv_reg_fault_state()4899 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v12_0_set_priv_reg_fault_state()4913 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v12_0_set_priv_reg_fault_state()4936 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v12_0_set_bad_op_fault_state()4945 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v12_0_set_bad_op_fault_state()4959 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v12_0_set_bad_op_fault_state()4981 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v12_0_set_priv_inst_fault_state()4990 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v12_0_set_priv_inst_fault_state()
3105 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v9_4_3_xcc_set_compute_eop_interrupt_state()3152 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v9_4_3_set_priv_reg_fault_state()3156 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v9_4_3_set_priv_reg_fault_state()3166 state == AMDGPU_IRQ_STATE_ENABLE ? in gfx_v9_4_3_set_priv_reg_fault_state()3192 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v9_4_3_set_bad_op_fault_state()3196 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v9_4_3_set_bad_op_fault_state()3206 state == AMDGPU_IRQ_STATE_ENABLE ? in gfx_v9_4_3_set_bad_op_fault_state()3231 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v9_4_3_set_priv_inst_fault_state()3235 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v9_4_3_set_priv_inst_fault_state()
999 case AMDGPU_IRQ_STATE_ENABLE: in sdma_v2_4_set_trap_irq_state()1015 case AMDGPU_IRQ_STATE_ENABLE: in sdma_v2_4_set_trap_irq_state()
555 if (state == AMDGPU_IRQ_STATE_ENABLE) in vce_v2_0_set_interrupt_state()
323 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in vpe_v6_1_set_trap_irq_state()
491 (state == AMDGPU_IRQ_STATE_ENABLE) ? 0 : 1); in nbif_v6_3_1_set_ras_err_event_athub_irq_state()
542 state = AMDGPU_IRQ_STATE_ENABLE; in amdgpu_irq_update()
1100 case AMDGPU_IRQ_STATE_ENABLE: in cik_sdma_set_trap_irq_state()1116 case AMDGPU_IRQ_STATE_ENABLE: in cik_sdma_set_trap_irq_state()
5939 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v9_0_set_gfx_eop_interrupt_state()5942 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v9_0_set_gfx_eop_interrupt_state()5991 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v9_0_set_compute_eop_interrupt_state()6037 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v9_0_set_priv_reg_fault_state()6040 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v9_0_set_priv_reg_fault_state()6050 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v9_0_set_priv_reg_fault_state()6073 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v9_0_set_bad_op_fault_state()6076 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v9_0_set_bad_op_fault_state()6106 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v9_0_set_priv_inst_fault_state()6109 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v9_0_set_priv_inst_fault_state()[all …]
573 (state == AMDGPU_IRQ_STATE_ENABLE) ? 0 : 1); in nbio_v4_3_set_ras_err_event_athub_irq_state()
1337 case AMDGPU_IRQ_STATE_ENABLE: in sdma_v3_0_set_trap_irq_state()1353 case AMDGPU_IRQ_STATE_ENABLE: in sdma_v3_0_set_trap_irq_state()
6324 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v11_0_set_gfx_eop_interrupt_state()6381 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v11_0_set_compute_eop_interrupt_state()6487 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v11_0_set_priv_reg_fault_state()6496 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v11_0_set_priv_reg_fault_state()6510 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v11_0_set_priv_reg_fault_state()6533 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v11_0_set_bad_op_fault_state()6542 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v11_0_set_bad_op_fault_state()6556 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v11_0_set_bad_op_fault_state()6578 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v11_0_set_priv_inst_fault_state()6587 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v11_0_set_priv_inst_fault_state()
442 case AMDGPU_IRQ_STATE_ENABLE: in gmc_v9_0_ecc_interrupt_state()508 case AMDGPU_IRQ_STATE_ENABLE: in gmc_v9_0_vm_fault_interrupt_state()
80 case AMDGPU_IRQ_STATE_ENABLE: in gmc_v11_0_vm_fault_interrupt_state()
70 case AMDGPU_IRQ_STATE_ENABLE: in gmc_v12_0_vm_fault_interrupt_state()
3199 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v6_0_set_gfx_eop_interrupt_state()3228 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v6_0_set_compute_eop_interrupt_state()3262 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v6_0_set_priv_reg_fault_state()3287 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v6_0_set_priv_inst_fault_state()
733 if (state == AMDGPU_IRQ_STATE_ENABLE) in vce_v3_0_set_interrupt_state()
779 if (state == AMDGPU_IRQ_STATE_ENABLE) in vce_v4_0_set_interrupt_state()
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