Searched refs:APBC_PWM0 (Results 1 – 4 of 4) sorted by relevance
| /drivers/clk/mmp/ |
| A D | clk-pxa1908-apbc.c | 14 #define APBC_PWM0 0xc macro
53 …{PXA1908_CLK_PWM0, "pwm0_clk", "pwm01_apb_share", CLK_SET_RATE_PARENT, APBC_PWM0, 0x2, 2, 0, 0, &p…
79 pxa_unit->base + APBC_PWM0, in pxa1908_apb_periph_clk_init()
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| A D | clk-of-pxa168.c | 25 #define APBC_PWM0 0xc macro
166 …{0, "pwm0_mux", pwm_parent_names, ARRAY_SIZE(pwm_parent_names), CLK_SET_RATE_PARENT, APBC_PWM0, 4,…
187 …{PXA168_CLK_PWM0, "pwm0_clk", "pwm0_mux", CLK_SET_RATE_PARENT, APBC_PWM0, 0x3, 0x3, 0x0, 0, &pwm0_…
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| A D | clk-of-pxa910.c | 28 #define APBC_PWM0 0xc macro
145 …{PXA910_CLK_PWM0, "pwm0_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM0, 0x3, 0x3, 0x0, 0, &reset_…
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| A D | clk-of-mmp2.c | 39 #define APBC_PWM0 0x3c macro
260 …{MMP2_CLK_PWM0, "pwm0_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM0, 0x7, 0x3, 0x0, 0, &reset_lo…
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