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Searched refs:ARRAY_MODE (Results 1 – 16 of 16) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
A Dgfx_v6_0.c423 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v6_0_tiling_mode_table_init()
431 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v6_0_tiling_mode_table_init()
439 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v6_0_tiling_mode_table_init()
447 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v6_0_tiling_mode_table_init()
455 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in gfx_v6_0_tiling_mode_table_init()
458 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v6_0_tiling_mode_table_init()
466 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v6_0_tiling_mode_table_init()
474 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v6_0_tiling_mode_table_init()
483 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in gfx_v6_0_tiling_mode_table_init()
486 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v6_0_tiling_mode_table_init()
[all …]
A Dgfx_v8_0.c2078 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init()
2082 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init()
2086 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init()
2090 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init()
2094 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init()
2098 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init()
2106 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | in gfx_v8_0_tiling_mode_table_init()
2108 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init()
2250 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init()
2254 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init()
[all …]
A Dgfx_v7_0.c1025 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v7_0_tiling_mode_table_init()
1029 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v7_0_tiling_mode_table_init()
1033 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v7_0_tiling_mode_table_init()
1037 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v7_0_tiling_mode_table_init()
1041 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v7_0_tiling_mode_table_init()
1045 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in gfx_v7_0_tiling_mode_table_init()
1053 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | in gfx_v7_0_tiling_mode_table_init()
1055 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in gfx_v7_0_tiling_mode_table_init()
1192 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v7_0_tiling_mode_table_init()
1196 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v7_0_tiling_mode_table_init()
[all …]
A Dcikd.h195 # define ARRAY_MODE(x) ((x) << 2) macro
A Ddce_v8_0.c1925 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { in dce_v8_0_crtc_do_set_base()
1941 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { in dce_v8_0_crtc_do_set_base()
A Damdgpu_display.c950 if (AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) == 1) /* LINEAR_ALIGNED */ in check_tiling_flags_gfx6()
A Ddce_v6_0.c2013 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { in dce_v6_0_crtc_do_set_base()
2028 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { in dce_v6_0_crtc_do_set_base()
A Ddce_v10_0.c1986 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { in dce_v10_0_crtc_do_set_base()
2006 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { in dce_v10_0_crtc_do_set_base()
A Ddce_v11_0.c2036 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { in dce_v11_0_crtc_do_set_base()
2056 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { in dce_v11_0_crtc_do_set_base()
/drivers/gpu/drm/radeon/
A Dcik.c2357 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2361 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2365 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2369 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2373 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2377 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in cik_tiling_mode_table_init()
2388 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | in cik_tiling_mode_table_init()
2390 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in cik_tiling_mode_table_init()
2500 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2504 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
[all …]
A Dsi.c2496 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in si_tiling_mode_table_init()
2505 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in si_tiling_mode_table_init()
2514 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in si_tiling_mode_table_init()
2523 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in si_tiling_mode_table_init()
2532 tile[4] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in si_tiling_mode_table_init()
2541 tile[5] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in si_tiling_mode_table_init()
2550 tile[6] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in si_tiling_mode_table_init()
2559 tile[7] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in si_tiling_mode_table_init()
2568 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | in si_tiling_mode_table_init()
2577 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in si_tiling_mode_table_init()
[all …]
A Dsid.h1180 # define ARRAY_MODE(x) ((x) << 2) macro
A Dcikd.h1218 # define ARRAY_MODE(x) ((x) << 2) macro
/drivers/gpu/drm/amd/display/amdgpu_dm/
A Damdgpu_dm_plane.c184 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) { in amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags()
204 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) in amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags()
A Damdgpu_dm.c11237 linear = AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_2D_TILED_THIN1 && in dm_check_cursor_fb()
11238 AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_1D_TILED_THIN1 && in dm_check_cursor_fb()
/drivers/gpu/drm/amd/include/
A Dnavi10_enum.h1673 typedef enum ARRAY_MODE { enum
1690 } ARRAY_MODE; typedef

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