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Searched refs:ASSERT (Results 1 – 25 of 204) sorted by relevance

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/drivers/gpu/drm/amd/display/dc/dml2/
A Ddml_display_rq_dlg_calc.c133 ASSERT(pte_row_height_linear >= 8); in dml_rq_dlg_get_rq_reg()
140 ASSERT(p1_pte_row_height_linear >= 8); in dml_rq_dlg_get_rq_reg()
282 ASSERT(refclk_freq_in_mhz != 0); in dml_rq_dlg_get_dlg_reg()
283 ASSERT(pclk_freq_in_mhz != 0); in dml_rq_dlg_get_dlg_reg()
284 ASSERT(ref_freq_to_pix_freq < 4.0); in dml_rq_dlg_get_dlg_reg()
358 ASSERT(dst_y_per_vm_vblank < max_dst_y_per_vm_vblank); in dml_rq_dlg_get_dlg_reg()
401 ASSERT(num_cursors <= 1); in dml_rq_dlg_get_dlg_reg()
504 ASSERT(refcyc_per_req_delivery_pre_l < dml_pow(2, 13)); in dml_rq_dlg_get_dlg_reg()
505 ASSERT(refcyc_per_req_delivery_l < dml_pow(2, 13)); in dml_rq_dlg_get_dlg_reg()
506 ASSERT(refcyc_per_req_delivery_pre_c < dml_pow(2, 13)); in dml_rq_dlg_get_dlg_reg()
[all …]
A Ddml2_dc_resource_mgmt.c91 ASSERT(false); in find_disp_cfg_idx_by_plane_id()
104 ASSERT(false); in find_disp_cfg_idx_by_stream_id()
523 ASSERT(false); in calculate_odm_slices()
657 ASSERT(false); in assign_pipes_to_plane()
765 ASSERT(false); in map_pipes_for_plane()
818 ASSERT(false); in get_target_mpc_factor()
824 ASSERT(false); in get_target_mpc_factor()
840 ASSERT(false); in get_target_mpc_factor()
893 ASSERT(false); in get_target_odm_factor()
1093 ASSERT(false); in dml2_map_dc_pipes()
[all …]
/drivers/gpu/drm/amd/display/dc/dml/dcn32/
A Ddisplay_rq_dlg_calc_32.c135 ASSERT(pte_row_height_linear >= 8); in dml32_rq_dlg_get_rq_reg()
144 ASSERT(p1_pte_row_height_linear >= 8); in dml32_rq_dlg_get_rq_reg()
273 ASSERT(ref_freq_to_pix_freq < 4.0); in dml32_rq_dlg_get_dlg_reg()
371 ASSERT(dst_y_per_vm_vblank < max_dst_y_per_vm_vblank); in dml32_rq_dlg_get_dlg_reg()
427 ASSERT(src->num_cursors <= 1); in dml32_rq_dlg_get_dlg_reg()
555 ASSERT(refcyc_per_req_delivery_pre_l < dml_pow(2, 13)); in dml32_rq_dlg_get_dlg_reg()
556 ASSERT(refcyc_per_req_delivery_l < dml_pow(2, 13)); in dml32_rq_dlg_get_dlg_reg()
558 ASSERT(refcyc_per_req_delivery_c < dml_pow(2, 13)); in dml32_rq_dlg_get_dlg_reg()
607 ASSERT(ttu_regs->qos_level_low_wm < dml_pow(2, 14)); in dml32_rq_dlg_get_dlg_reg()
608 ASSERT(ttu_regs->qos_level_high_wm < dml_pow(2, 14)); in dml32_rq_dlg_get_dlg_reg()
[all …]
/drivers/gpu/drm/amd/display/dc/basics/
A Dbw_fixed.c53 ASSERT(value < BW_FIXED_MAX_I32 && value > BW_FIXED_MIN_I32); in bw_int_to_fixed_nonconst()
70 ASSERT(denominator != 0); in bw_frc_to_fixed()
76 ASSERT(res_value <= BW_FIXED_MAX_I32); in bw_frc_to_fixed()
98 ASSERT(res_value <= MAX_I64 - summand); in bw_frc_to_fixed()
118 ASSERT(abs_i64(result.value) <= abs_i64(arg.value)); in bw_floor2()
159 ASSERT(res.value <= BW_FIXED_MAX_I32); in bw_mul()
165 ASSERT(tmp <= (uint64_t)(MAX_I64 - res.value)); in bw_mul()
171 ASSERT(tmp <= (uint64_t)(MAX_I64 - res.value)); in bw_mul()
180 ASSERT(tmp <= (uint64_t)(MAX_I64 - res.value)); in bw_mul()
A Dfixpt31_32.c86 ASSERT(res_value <= LONG_MAX); in dc_fixpt_from_fraction()
108 ASSERT(res_value <= LLONG_MAX - summand); in dc_fixpt_from_fraction()
145 ASSERT(tmp <= (unsigned long long)(LLONG_MAX - res.value)); in dc_fixpt_mul()
151 ASSERT(tmp <= (unsigned long long)(LLONG_MAX - res.value)); in dc_fixpt_mul()
160 ASSERT(tmp <= (unsigned long long)(LLONG_MAX - res.value)); in dc_fixpt_mul()
188 ASSERT(tmp <= (unsigned long long)(LLONG_MAX - res.value)); in dc_fixpt_sqr()
192 ASSERT(tmp <= (unsigned long long)(LLONG_MAX - res.value)); in dc_fixpt_sqr()
311 ASSERT(dc_fixpt_lt(arg, dc_fixpt_one)); in fixed31_32_exp_from_taylor_series()
353 ASSERT(m != 0); in dc_fixpt_exp()
355 ASSERT(dc_fixpt_lt( in dc_fixpt_exp()
[all …]
/drivers/gpu/drm/amd/display/dc/dml/
A Ddml1_display_rq_dlg_calc.c183 ASSERT(prefill > 0.0 && prefill <= 8.0); in get_swath_need()
526 ASSERT(log2_dpte_row_height_linear >= 3); in dml1_rq_dlg_get_row_heights()
852 ASSERT(log2_dpte_row_height_linear >= 3); in get_surf_rq_param()
947 ASSERT(0); in get_surf_rq_param()
955 ASSERT(0); in get_surf_rq_param()
1151 ASSERT(ref_freq_to_pix_freq < 4.0); in dml1_rq_dlg_get_dlg_params()
1346 ASSERT(dst_y_prefetch >= 2.0); in dml1_rq_dlg_get_dlg_params()
1517 ASSERT(vratio_pre_l <= 4.0); in dml1_rq_dlg_get_dlg_params()
1523 ASSERT(vratio_pre_c <= 4.0); in dml1_rq_dlg_get_dlg_params()
1776 ASSERT(refcyc_per_req_delivery_l < dml_pow(2, 13)); in dml1_rq_dlg_get_dlg_params()
[all …]
/drivers/gpu/drm/amd/display/dc/dml/dcn31/
A Ddisplay_rq_dlg_calc_31.c582 ASSERT(log2_dpte_row_height_linear >= 3); in get_meta_and_pte_attr()
795 ASSERT(cur_src_width <= 256); in calculate_ttu_cursor()
826 ASSERT(*refcyc_per_req_delivery_pre_cur < dml_pow(2, 13)); in calculate_ttu_cursor()
841 ASSERT(*refcyc_per_req_delivery_cur < dml_pow(2, 13)); in calculate_ttu_cursor()
1116 …ASSERT(dst_y_per_vm_vblank < max_dst_y_per_vm_vblank); ASSERT(dst_y_per_row_vblank < max_dst_y_per… in dml_rq_dlg_get_dlg_params()
1318 …ASSERT(refcyc_per_req_delivery_pre_l < dml_pow(2, 13)); ASSERT(refcyc_per_req_delivery_l < dml_pow… in dml_rq_dlg_get_dlg_params()
1355 …ASSERT(refcyc_per_req_delivery_pre_c < dml_pow(2, 13)); ASSERT(refcyc_per_req_delivery_c < dml_pow… in dml_rq_dlg_get_dlg_params()
1362 ASSERT(src->num_cursors <= 1); in dml_rq_dlg_get_dlg_params()
1523 ASSERT(disp_ttu_regs->qos_level_low_wm < dml_pow(2, 14)); in dml_rq_dlg_get_dlg_params()
1526 ASSERT(disp_ttu_regs->qos_level_high_wm < dml_pow(2, 14)); in dml_rq_dlg_get_dlg_params()
[all …]
/drivers/gpu/drm/amd/display/dc/dml/dcn21/
A Ddisplay_rq_dlg_calc_21.c611 ASSERT(log2_dpte_row_height_linear >= 3); in get_meta_and_pte_attr()
964 ASSERT(ref_freq_to_pix_freq < 4.0); in dml_rq_dlg_get_dlg_params()
1167 ASSERT(dst_y_per_vm_vblank < max_dst_y_per_vm_vblank); in dml_rq_dlg_get_dlg_params()
1168 ASSERT(dst_y_per_row_vblank < max_dst_y_per_row_vblank); in dml_rq_dlg_get_dlg_params()
1368 ASSERT(refcyc_per_req_delivery_pre_l < dml_pow(2, 13)); in dml_rq_dlg_get_dlg_params()
1369 ASSERT(refcyc_per_req_delivery_l < dml_pow(2, 13)); in dml_rq_dlg_get_dlg_params()
1405 ASSERT(refcyc_per_req_delivery_c < dml_pow(2, 13)); in dml_rq_dlg_get_dlg_params()
1481 ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_c in dml_rq_dlg_get_dlg_params()
1631 ASSERT(disp_ttu_regs->min_ttu_vblank < dml_pow(2, 24)); in dml_rq_dlg_get_dlg_params()
1712 ASSERT(cur_src_width <= 256); in calculate_ttu_cursor()
[all …]
/drivers/gpu/drm/amd/display/dc/dml/dcn20/
A Ddisplay_rq_dlg_calc_20.c610 ASSERT(log2_dpte_row_height_linear >= 3); in get_meta_and_pte_attr()
918 ASSERT(ref_freq_to_pix_freq < 4.0); in dml20_rq_dlg_get_dlg_params()
1115 ASSERT(dst_y_per_vm_vblank < min_dst_y_per_vm_vblank); in dml20_rq_dlg_get_dlg_params()
1116 ASSERT(dst_y_per_row_vblank < min_dst_y_per_row_vblank); in dml20_rq_dlg_get_dlg_params()
1304 ASSERT(refcyc_per_req_delivery_pre_l < dml_pow(2, 13)); in dml20_rq_dlg_get_dlg_params()
1305 ASSERT(refcyc_per_req_delivery_l < dml_pow(2, 13)); in dml20_rq_dlg_get_dlg_params()
1337 ASSERT(refcyc_per_req_delivery_c < dml_pow(2, 13)); in dml20_rq_dlg_get_dlg_params()
1398 ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_c in dml20_rq_dlg_get_dlg_params()
1523 ASSERT(disp_ttu_regs->min_ttu_vblank < dml_pow(2, 24)); in dml20_rq_dlg_get_dlg_params()
1598 ASSERT(cur_src_width <= 256); in calculate_ttu_cursor()
[all …]
A Ddisplay_rq_dlg_calc_20v2.c610 ASSERT(log2_dpte_row_height_linear >= 3); in get_meta_and_pte_attr()
918 ASSERT(ref_freq_to_pix_freq < 4.0); in dml20v2_rq_dlg_get_dlg_params()
1116 ASSERT(dst_y_per_vm_vblank < min_dst_y_per_vm_vblank); in dml20v2_rq_dlg_get_dlg_params()
1117 ASSERT(dst_y_per_row_vblank < min_dst_y_per_row_vblank); in dml20v2_rq_dlg_get_dlg_params()
1305 ASSERT(refcyc_per_req_delivery_pre_l < dml_pow(2, 13)); in dml20v2_rq_dlg_get_dlg_params()
1306 ASSERT(refcyc_per_req_delivery_l < dml_pow(2, 13)); in dml20v2_rq_dlg_get_dlg_params()
1338 ASSERT(refcyc_per_req_delivery_c < dml_pow(2, 13)); in dml20v2_rq_dlg_get_dlg_params()
1399 ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_c in dml20v2_rq_dlg_get_dlg_params()
1524 ASSERT(disp_ttu_regs->min_ttu_vblank < dml_pow(2, 24)); in dml20v2_rq_dlg_get_dlg_params()
1599 ASSERT(cur_src_width <= 256); in calculate_ttu_cursor()
[all …]
/drivers/gpu/drm/amd/display/dc/dml/dcn30/
A Ddisplay_rq_dlg_calc_30.c581 ASSERT(log2_dpte_row_height_linear >= 3); in get_meta_and_pte_attr()
814 ASSERT(cur_src_width <= 256); in calculate_ttu_cursor()
879 ASSERT(*refcyc_per_req_delivery_cur < dml_pow(2, 13)); in calculate_ttu_cursor()
1035 ASSERT(ref_freq_to_pix_freq < 4.0); in dml_rq_dlg_get_dlg_params()
1271 ASSERT(dst_y_per_vm_vblank < max_dst_y_per_vm_vblank); in dml_rq_dlg_get_dlg_params()
1272 ASSERT(dst_y_per_row_vblank < max_dst_y_per_row_vblank); in dml_rq_dlg_get_dlg_params()
1475 ASSERT(refcyc_per_req_delivery_pre_l < dml_pow(2, 13)); in dml_rq_dlg_get_dlg_params()
1476 ASSERT(refcyc_per_req_delivery_l < dml_pow(2, 13)); in dml_rq_dlg_get_dlg_params()
1508 ASSERT(refcyc_per_req_delivery_c < dml_pow(2, 13)); in dml_rq_dlg_get_dlg_params()
1575 ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_c in dml_rq_dlg_get_dlg_params()
[all …]
/drivers/gpu/drm/amd/display/dc/dml/dcn314/
A Ddisplay_rq_dlg_calc_314.c670 ASSERT(log2_dpte_row_height_linear >= 3); in get_meta_and_pte_attr()
882 ASSERT(cur_src_width <= 256); in calculate_ttu_cursor()
926 ASSERT(*refcyc_per_req_delivery_cur < dml_pow(2, 13)); in calculate_ttu_cursor()
1204 …ASSERT(dst_y_per_vm_vblank < max_dst_y_per_vm_vblank); ASSERT(dst_y_per_row_vblank < max_dst_y_per… in dml_rq_dlg_get_dlg_params()
1406 …ASSERT(refcyc_per_req_delivery_pre_l < dml_pow(2, 13)); ASSERT(refcyc_per_req_delivery_l < dml_pow… in dml_rq_dlg_get_dlg_params()
1443 …ASSERT(refcyc_per_req_delivery_pre_c < dml_pow(2, 13)); ASSERT(refcyc_per_req_delivery_c < dml_pow… in dml_rq_dlg_get_dlg_params()
1450 ASSERT(src->num_cursors <= 1); in dml_rq_dlg_get_dlg_params()
1489 ASSERT(disp_dlg_regs->dst_y_after_scaler < 8); in dml_rq_dlg_get_dlg_params()
1611 ASSERT(disp_ttu_regs->qos_level_low_wm < dml_pow(2, 14)); in dml_rq_dlg_get_dlg_params()
1614 ASSERT(disp_ttu_regs->qos_level_high_wm < dml_pow(2, 14)); in dml_rq_dlg_get_dlg_params()
[all …]
/drivers/gpu/drm/amd/display/include/
A Dfixed31_32.h212 ASSERT(((arg.value >= 0) && (arg.value <= LLONG_MAX >> shift)) || in dc_fixpt_shl()
249 ASSERT(((arg1.value >= 0) && (LLONG_MAX - arg1.value >= arg2.value)) || in dc_fixpt_add()
274 ASSERT(((arg2.value >= 0) && (LLONG_MIN + arg2.value <= arg1.value)) || in dc_fixpt_sub()
466 ASSERT(LLONG_MAX - (long long)arg_value >= summand); in dc_fixpt_round()
487 ASSERT(LLONG_MAX - (long long)arg_value >= summand); in dc_fixpt_ceil()
522 ASSERT(frac_bits == FIXED31_32_BITS_PER_FRACTIONAL_PART); in dc_fixpt_truncate()
/drivers/gpu/drm/amd/display/dc/link/hwss/
A Dlink_hwss_dio.c57 ASSERT(link_enc); in setup_dio_stream_encoder()
87 ASSERT(link_enc); in reset_dio_stream_encoder()
164 ASSERT(link_enc); in enable_dio_dp_link_output()
191 ASSERT(link_enc); in disable_dio_link_output()
209 ASSERT(link_enc); in set_dio_dp_link_test_pattern()
227 ASSERT(link_enc); in set_dio_dp_lane_settings()
243 ASSERT(link_enc); in update_dio_stream_allocation_table()
/drivers/gpu/drm/amd/display/dc/mpc/dcn10/
A Ddcn10_mpc.c53 ASSERT(bottommost_mpcc != bottommost_mpcc->mpcc_bot); in mpc1_set_bg_color()
113 ASSERT(!(mpc10->mpcc_in_use_mask & 1 << id)); in mpc1_assert_idle_mpcc()
123 ASSERT(mpcc_id < mpc10->num_mpcc); in mpc1_get_mpcc()
136 ASSERT(tmp_mpcc != tmp_mpcc->mpcc_bot); in mpc1_get_mpcc_for_dpp()
158 ASSERT(mpc_busy == 0); in mpc1_assert_mpcc_idle_before_connect()
159 ASSERT(mpc_idle == 1); in mpc1_assert_mpcc_idle_before_connect()
192 ASSERT(mpcc_id < mpc10->num_mpcc); in mpc1_insert_plane()
193 ASSERT(!(mpc10->mpcc_in_use_mask & 1 << mpcc_id)); in mpc1_insert_plane()
/drivers/gpu/drm/amd/display/dc/dsc/dcn20/
A Ddcn20_dsc.c191 ASSERT(is_config_ok); in dsc2_set_config()
211 ASSERT(is_config_ok); in dsc2_get_packed_pps()
232 ASSERT(0); in dsc2_enable()
369 ASSERT(dsc_cfg->dc_dsc_cfg.num_slices_h); in dsc_prepare_config()
370 ASSERT(dsc_cfg->dc_dsc_cfg.num_slices_v); in dsc_prepare_config()
371 ASSERT(dsc_cfg->dc_dsc_cfg.version_minor == 1 || dsc_cfg->dc_dsc_cfg.version_minor == 2); in dsc_prepare_config()
372 ASSERT(dsc_cfg->pic_width); in dsc_prepare_config()
373 ASSERT(dsc_cfg->pic_height); in dsc_prepare_config()
374 ASSERT((dsc_cfg->dc_dsc_cfg.version_minor == 1 && in dsc_prepare_config()
414 ASSERT(dsc_reg_vals->pps.slice_height * dsc_cfg->dc_dsc_cfg.num_slices_v == dsc_cfg->pic_height); in dsc_prepare_config()
[all …]
/drivers/gpu/drm/amd/display/dc/dio/dcn30/
A Ddcn30_dio_stream_encoder.c568 ASSERT(crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB); in enc3_stream_encoder_dvi_set_stream_attribute()
569 ASSERT(crtc_timing->display_color_depth == COLOR_DEPTH_888); in enc3_stream_encoder_dvi_set_stream_attribute()
699 ASSERT (enc->afmt); in enc3_stream_encoder_hdmi_set_stream_attribute()
714 ASSERT (enc->afmt); in enc3_audio_mute_control()
723 ASSERT (enc->afmt); in enc3_se_dp_audio_setup()
745 ASSERT (enc->afmt); in enc3_se_setup_dp_audio()
766 ASSERT (enc->afmt); in enc3_se_setup_hdmi_audio()
823 ASSERT (enc->afmt); in enc3_se_hdmi_audio_setup()
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/
A Drn_clk_mgr_vbios_smu.c126 ASSERT(0); in rn_vbios_smu_send_msg_with_param()
162 ASSERT(actual_dispclk_set_mhz >= khz_to_mhz_ceil(requested_dispclk_khz)); in rn_vbios_smu_set_dispclk()
214 ASSERT(actual_dppclk_set_mhz >= khz_to_mhz_ceil(requested_dpp_khz)); in rn_vbios_smu_set_dppclk()
/drivers/gpu/drm/amd/display/dc/core/
A Ddc_stat.c59 ASSERT(status == DMUB_STATUS_OK); in dc_stat_get_dmub_notification()
89 ASSERT(status == DMUB_STATUS_OK); in dc_stat_get_dmub_dataout()
/drivers/gpu/drm/amd/display/dc/mpc/dcn20/
A Ddcn20_mpc.c476 ASSERT(!(mpc20->mpcc_in_use_mask & 1 << id)); in mpc2_assert_idle_mpcc()
500 ASSERT(!mpc_busy); in mpc2_assert_mpcc_idle_before_connect()
501 ASSERT(mpc_idle); in mpc2_assert_mpcc_idle_before_connect()
502 ASSERT(mpc_disabled); in mpc2_assert_mpcc_idle_before_connect()
504 ASSERT(!mpc_disabled); in mpc2_assert_mpcc_idle_before_connect()
505 ASSERT(!mpc_idle); in mpc2_assert_mpcc_idle_before_connect()
534 ASSERT(tmp_mpcc != tmp_mpcc->mpcc_bot); in mpc2_get_mpcc_for_dpp()
/drivers/gpu/drm/amd/display/dc/dio/dcn35/
A Ddcn35_dio_stream_encoder.c85 ASSERT(crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB); in enc35_stream_encoder_dvi_set_stream_attribute()
86 ASSERT(crtc_timing->display_color_depth == COLOR_DEPTH_888); in enc35_stream_encoder_dvi_set_stream_attribute()
210 ASSERT(enc->afmt); in enc35_stream_encoder_hdmi_set_stream_attribute()
374 ASSERT(stream_enc_inst < 5 && link_enc_inst < 5); in enc35_stream_encoder_map_to_link()
/drivers/gpu/drm/amd/display/dc/dml/calcs/
A Ddcn_calc_math.c73 ASSERT(significance != 0); in dcn_bw_floor2()
89 ASSERT(significance != 0); in dcn_bw_ceil2()
/drivers/gpu/drm/amd/display/dc/hwss/dcn30/
A Ddcn30_hwseq.c434 ASSERT(wb_info->dwb_pipe_inst < MAX_DWB_PIPES); in dcn30_set_writeback()
435 ASSERT(wb_info->wb_enabled); in dcn30_set_writeback()
436 ASSERT(wb_info->mpcc_inst >= 0); in dcn30_set_writeback()
437 ASSERT(wb_info->mpcc_inst < dc->res_pool->mpcc_count); in dcn30_set_writeback()
557 ASSERT(dwb_pipe_inst < MAX_DWB_PIPES); in dcn30_disable_writeback()
582 ASSERT(stream); in dcn30_program_all_writeback_pipes_in_tree()
589 ASSERT(stream_status); in dcn30_program_all_writeback_pipes_in_tree()
591 ASSERT(stream->num_wb_info <= dc->res_pool->res_cap->num_dwb); in dcn30_program_all_writeback_pipes_in_tree()
621 ASSERT(wb_info.dwb_pipe_inst < dc->res_pool->res_cap->num_dwb); in dcn30_program_all_writeback_pipes_in_tree()
855 ASSERT(pipe_ctx->stream); in dcn30_update_info_frame()
[all …]
/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_standalone_libraries/
A Dlib_float_math.c7 #define ASSERT(condition) macro
49 ASSERT(significance != 0); in math_floor2()
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/
A Ddcn316_clk_mgr.c387 ASSERT(num_valid_sets != 0); /* Must have at least one set of valid watermarks */ in dcn316_build_watermark_ranges()
478 ASSERT(clock); in find_clk_for_voltage()
507 ASSERT(0); in dcn316_clk_mgr_helper_populate_bw_params()
519 ASSERT(0); in dcn316_clk_mgr_helper_populate_bw_params()
610 ASSERT(clk_mgr->smu_wm_set.wm_set); in dcn316_clk_mgr_construct()
623 ASSERT(smu_dpm_clks.dpm_clks); in dcn316_clk_mgr_construct()

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