1 /*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
14 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
15 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
16 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
17 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
18 * USE OR OTHER DEALINGS IN THE SOFTWARE.
19 *
20 * The above copyright notice and this permission notice (including the
21 * next paragraph) shall be included in all copies or substantial portions
22 * of the Software.
23 *
24 */
25 /*
26 * Authors: Dave Airlie <airlied@redhat.com>
27 */
28 #ifndef __AST_DRV_H__
29 #define __AST_DRV_H__
30
31 #include <linux/io.h>
32 #include <linux/types.h>
33
34 #include <drm/drm_connector.h>
35 #include <drm/drm_crtc.h>
36 #include <drm/drm_encoder.h>
37 #include <drm/drm_mode.h>
38 #include <drm/drm_framebuffer.h>
39
40 #include "ast_reg.h"
41
42 struct ast_vbios_enhtable;
43
44 #define DRIVER_AUTHOR "Dave Airlie"
45
46 #define DRIVER_NAME "ast"
47 #define DRIVER_DESC "AST"
48
49 #define DRIVER_MAJOR 0
50 #define DRIVER_MINOR 1
51 #define DRIVER_PATCHLEVEL 0
52
53 #define PCI_CHIP_AST2000 0x2000
54 #define PCI_CHIP_AST2100 0x2010
55
56 #define __AST_CHIP(__gen, __index) ((__gen) << 16 | (__index))
57
58 enum ast_chip {
59 /* 1st gen */
60 AST1000 = __AST_CHIP(1, 0), // unused
61 AST2000 = __AST_CHIP(1, 1),
62 /* 2nd gen */
63 AST1100 = __AST_CHIP(2, 0),
64 AST2100 = __AST_CHIP(2, 1),
65 AST2050 = __AST_CHIP(2, 2), // unused
66 /* 3rd gen */
67 AST2200 = __AST_CHIP(3, 0),
68 AST2150 = __AST_CHIP(3, 1),
69 /* 4th gen */
70 AST2300 = __AST_CHIP(4, 0),
71 AST1300 = __AST_CHIP(4, 1),
72 AST1050 = __AST_CHIP(4, 2), // unused
73 /* 5th gen */
74 AST2400 = __AST_CHIP(5, 0),
75 AST1400 = __AST_CHIP(5, 1),
76 AST1250 = __AST_CHIP(5, 2), // unused
77 /* 6th gen */
78 AST2500 = __AST_CHIP(6, 0),
79 AST2510 = __AST_CHIP(6, 1),
80 AST2520 = __AST_CHIP(6, 2), // unused
81 /* 7th gen */
82 AST2600 = __AST_CHIP(7, 0),
83 AST2620 = __AST_CHIP(7, 1), // unused
84 };
85
86 #define __AST_CHIP_GEN(__chip) (((unsigned long)(__chip)) >> 16)
87
88 enum ast_tx_chip {
89 AST_TX_NONE,
90 AST_TX_SIL164,
91 AST_TX_DP501,
92 AST_TX_ASTDP,
93 };
94
95 enum ast_config_mode {
96 ast_use_p2a,
97 ast_use_dt,
98 ast_use_defaults
99 };
100
101 #define AST_DRAM_512Mx16 0
102 #define AST_DRAM_1Gx16 1
103 #define AST_DRAM_512Mx32 2
104 #define AST_DRAM_1Gx32 3
105 #define AST_DRAM_2Gx16 6
106 #define AST_DRAM_4Gx16 7
107 #define AST_DRAM_8Gx16 8
108
109 /*
110 * Hardware cursor
111 */
112
113 #define AST_MAX_HWC_WIDTH 64
114 #define AST_MAX_HWC_HEIGHT 64
115 #define AST_HWC_PITCH (AST_MAX_HWC_WIDTH * SZ_2)
116 #define AST_HWC_SIZE (AST_MAX_HWC_HEIGHT * AST_HWC_PITCH)
117
118 /*
119 * Planes
120 */
121
122 struct ast_plane {
123 struct drm_plane base;
124
125 u64 offset;
126 unsigned long size;
127 };
128
to_ast_plane(struct drm_plane * plane)129 static inline struct ast_plane *to_ast_plane(struct drm_plane *plane)
130 {
131 return container_of(plane, struct ast_plane, base);
132 }
133
134 struct ast_cursor_plane {
135 struct ast_plane base;
136
137 u8 argb4444[AST_HWC_SIZE];
138 };
139
to_ast_cursor_plane(struct drm_plane * plane)140 static inline struct ast_cursor_plane *to_ast_cursor_plane(struct drm_plane *plane)
141 {
142 return container_of(to_ast_plane(plane), struct ast_cursor_plane, base);
143 }
144
145 /*
146 * Connector
147 */
148
149 struct ast_connector {
150 struct drm_connector base;
151
152 enum drm_connector_status physical_status;
153 };
154
155 static inline struct ast_connector *
to_ast_connector(struct drm_connector * connector)156 to_ast_connector(struct drm_connector *connector)
157 {
158 return container_of(connector, struct ast_connector, base);
159 }
160
161 /*
162 * Device
163 */
164
165 struct ast_device {
166 struct drm_device base;
167
168 void __iomem *regs;
169 void __iomem *ioregs;
170 void __iomem *dp501_fw_buf;
171
172 enum ast_config_mode config_mode;
173 enum ast_chip chip;
174
175 uint32_t dram_bus_width;
176 uint32_t dram_type;
177 uint32_t mclk;
178
179 void __iomem *vram;
180 unsigned long vram_base;
181 unsigned long vram_size;
182
183 struct mutex modeset_lock; /* Protects access to modeset I/O registers in ioregs */
184
185 enum ast_tx_chip tx_chip;
186
187 struct ast_plane primary_plane;
188 struct ast_cursor_plane cursor_plane;
189 struct drm_crtc crtc;
190 union {
191 struct {
192 struct drm_encoder encoder;
193 struct ast_connector connector;
194 } vga;
195 struct {
196 struct drm_encoder encoder;
197 struct ast_connector connector;
198 } sil164;
199 struct {
200 struct drm_encoder encoder;
201 struct ast_connector connector;
202 } dp501;
203 struct {
204 struct drm_encoder encoder;
205 struct ast_connector connector;
206 } astdp;
207 } output;
208
209 bool support_wsxga_p; /* 1680x1050 */
210 bool support_fullhd; /* 1920x1080 */
211 bool support_wuxga; /* 1920x1200 */
212
213 u8 *dp501_fw_addr;
214 const struct firmware *dp501_fw; /* dp501 fw */
215 };
216
to_ast_device(struct drm_device * dev)217 static inline struct ast_device *to_ast_device(struct drm_device *dev)
218 {
219 return container_of(dev, struct ast_device, base);
220 }
221
222 struct drm_device *ast_device_create(struct pci_dev *pdev,
223 const struct drm_driver *drv,
224 enum ast_chip chip,
225 enum ast_config_mode config_mode,
226 void __iomem *regs,
227 void __iomem *ioregs,
228 bool need_post);
229
__ast_gen(struct ast_device * ast)230 static inline unsigned long __ast_gen(struct ast_device *ast)
231 {
232 return __AST_CHIP_GEN(ast->chip);
233 }
234 #define AST_GEN(__ast) __ast_gen(__ast)
235
__ast_gen_is_eq(struct ast_device * ast,unsigned long gen)236 static inline bool __ast_gen_is_eq(struct ast_device *ast, unsigned long gen)
237 {
238 return __ast_gen(ast) == gen;
239 }
240 #define IS_AST_GEN1(__ast) __ast_gen_is_eq(__ast, 1)
241 #define IS_AST_GEN2(__ast) __ast_gen_is_eq(__ast, 2)
242 #define IS_AST_GEN3(__ast) __ast_gen_is_eq(__ast, 3)
243 #define IS_AST_GEN4(__ast) __ast_gen_is_eq(__ast, 4)
244 #define IS_AST_GEN5(__ast) __ast_gen_is_eq(__ast, 5)
245 #define IS_AST_GEN6(__ast) __ast_gen_is_eq(__ast, 6)
246 #define IS_AST_GEN7(__ast) __ast_gen_is_eq(__ast, 7)
247
__ast_read8(const void __iomem * addr,u32 reg)248 static inline u8 __ast_read8(const void __iomem *addr, u32 reg)
249 {
250 return ioread8(addr + reg);
251 }
252
__ast_read32(const void __iomem * addr,u32 reg)253 static inline u32 __ast_read32(const void __iomem *addr, u32 reg)
254 {
255 return ioread32(addr + reg);
256 }
257
__ast_write8(void __iomem * addr,u32 reg,u8 val)258 static inline void __ast_write8(void __iomem *addr, u32 reg, u8 val)
259 {
260 iowrite8(val, addr + reg);
261 }
262
__ast_write32(void __iomem * addr,u32 reg,u32 val)263 static inline void __ast_write32(void __iomem *addr, u32 reg, u32 val)
264 {
265 iowrite32(val, addr + reg);
266 }
267
__ast_read8_i(void __iomem * addr,u32 reg,u8 index)268 static inline u8 __ast_read8_i(void __iomem *addr, u32 reg, u8 index)
269 {
270 __ast_write8(addr, reg, index);
271 return __ast_read8(addr, reg + 1);
272 }
273
__ast_read8_i_masked(void __iomem * addr,u32 reg,u8 index,u8 read_mask)274 static inline u8 __ast_read8_i_masked(void __iomem *addr, u32 reg, u8 index, u8 read_mask)
275 {
276 u8 val = __ast_read8_i(addr, reg, index);
277
278 return val & read_mask;
279 }
280
__ast_write8_i(void __iomem * addr,u32 reg,u8 index,u8 val)281 static inline void __ast_write8_i(void __iomem *addr, u32 reg, u8 index, u8 val)
282 {
283 __ast_write8(addr, reg, index);
284 __ast_write8(addr, reg + 1, val);
285 }
286
__ast_write8_i_masked(void __iomem * addr,u32 reg,u8 index,u8 read_mask,u8 val)287 static inline void __ast_write8_i_masked(void __iomem *addr, u32 reg, u8 index, u8 read_mask,
288 u8 val)
289 {
290 u8 tmp = __ast_read8_i_masked(addr, reg, index, read_mask);
291
292 tmp |= val;
293 __ast_write8_i(addr, reg, index, tmp);
294 }
295
ast_read32(struct ast_device * ast,u32 reg)296 static inline u32 ast_read32(struct ast_device *ast, u32 reg)
297 {
298 return __ast_read32(ast->regs, reg);
299 }
300
ast_write32(struct ast_device * ast,u32 reg,u32 val)301 static inline void ast_write32(struct ast_device *ast, u32 reg, u32 val)
302 {
303 __ast_write32(ast->regs, reg, val);
304 }
305
ast_io_read8(struct ast_device * ast,u32 reg)306 static inline u8 ast_io_read8(struct ast_device *ast, u32 reg)
307 {
308 return __ast_read8(ast->ioregs, reg);
309 }
310
ast_io_write8(struct ast_device * ast,u32 reg,u8 val)311 static inline void ast_io_write8(struct ast_device *ast, u32 reg, u8 val)
312 {
313 __ast_write8(ast->ioregs, reg, val);
314 }
315
ast_get_index_reg(struct ast_device * ast,u32 base,u8 index)316 static inline u8 ast_get_index_reg(struct ast_device *ast, u32 base, u8 index)
317 {
318 return __ast_read8_i(ast->ioregs, base, index);
319 }
320
ast_get_index_reg_mask(struct ast_device * ast,u32 base,u8 index,u8 preserve_mask)321 static inline u8 ast_get_index_reg_mask(struct ast_device *ast, u32 base, u8 index,
322 u8 preserve_mask)
323 {
324 return __ast_read8_i_masked(ast->ioregs, base, index, preserve_mask);
325 }
326
ast_set_index_reg(struct ast_device * ast,u32 base,u8 index,u8 val)327 static inline void ast_set_index_reg(struct ast_device *ast, u32 base, u8 index, u8 val)
328 {
329 __ast_write8_i(ast->ioregs, base, index, val);
330 }
331
ast_set_index_reg_mask(struct ast_device * ast,u32 base,u8 index,u8 preserve_mask,u8 val)332 static inline void ast_set_index_reg_mask(struct ast_device *ast, u32 base, u8 index,
333 u8 preserve_mask, u8 val)
334 {
335 __ast_write8_i_masked(ast->ioregs, base, index, preserve_mask, val);
336 }
337
338 struct ast_vbios_stdtable {
339 u8 misc;
340 u8 seq[4];
341 u8 crtc[25];
342 u8 ar[20];
343 u8 gr[9];
344 };
345
346 struct ast_vbios_dclk_info {
347 u8 param1;
348 u8 param2;
349 u8 param3;
350 };
351
352 struct ast_crtc_state {
353 struct drm_crtc_state base;
354
355 /* Last known format of primary plane */
356 const struct drm_format_info *format;
357
358 const struct ast_vbios_stdtable *std_table;
359 const struct ast_vbios_enhtable *vmode;
360 };
361
362 #define to_ast_crtc_state(state) container_of(state, struct ast_crtc_state, base)
363
364 #define AST_MM_ALIGN_SHIFT 4
365 #define AST_MM_ALIGN_MASK ((1 << AST_MM_ALIGN_SHIFT) - 1)
366
367 #define AST_DP501_FW_VERSION_MASK GENMASK(7, 4)
368 #define AST_DP501_FW_VERSION_1 BIT(4)
369 #define AST_DP501_PNP_CONNECTED BIT(1)
370
371 #define AST_DP501_DEFAULT_DCLK 65
372
373 #define AST_DP501_GBL_VERSION 0xf000
374 #define AST_DP501_PNPMONITOR 0xf010
375 #define AST_DP501_LINKRATE 0xf014
376 #define AST_DP501_EDID_DATA 0xf020
377
378 /*
379 * ASTDP resoultion table:
380 * EX: ASTDP_A_B_C:
381 * A: Resolution
382 * B: Refresh Rate
383 * C: Misc information, such as CVT, Reduce Blanked
384 */
385 #define ASTDP_640x480_60 0x00
386 #define ASTDP_640x480_72 0x01
387 #define ASTDP_640x480_75 0x02
388 #define ASTDP_640x480_85 0x03
389 #define ASTDP_800x600_56 0x04
390 #define ASTDP_800x600_60 0x05
391 #define ASTDP_800x600_72 0x06
392 #define ASTDP_800x600_75 0x07
393 #define ASTDP_800x600_85 0x08
394 #define ASTDP_1024x768_60 0x09
395 #define ASTDP_1024x768_70 0x0A
396 #define ASTDP_1024x768_75 0x0B
397 #define ASTDP_1024x768_85 0x0C
398 #define ASTDP_1280x1024_60 0x0D
399 #define ASTDP_1280x1024_75 0x0E
400 #define ASTDP_1280x1024_85 0x0F
401 #define ASTDP_1600x1200_60 0x10
402 #define ASTDP_320x240_60 0x11
403 #define ASTDP_400x300_60 0x12
404 #define ASTDP_512x384_60 0x13
405 #define ASTDP_1920x1200_60 0x14
406 #define ASTDP_1920x1080_60 0x15
407 #define ASTDP_1280x800_60 0x16
408 #define ASTDP_1280x800_60_RB 0x17
409 #define ASTDP_1440x900_60 0x18
410 #define ASTDP_1440x900_60_RB 0x19
411 #define ASTDP_1680x1050_60 0x1A
412 #define ASTDP_1680x1050_60_RB 0x1B
413 #define ASTDP_1600x900_60 0x1C
414 #define ASTDP_1600x900_60_RB 0x1D
415 #define ASTDP_1366x768_60 0x1E
416 #define ASTDP_1152x864_75 0x1F
417
418 int ast_mm_init(struct ast_device *ast);
419
420 /* ast_2000.c */
421 int ast_2000_post(struct ast_device *ast);
422
423 /* ast_2100.c */
424 int ast_2100_post(struct ast_device *ast);
425
426 /* ast_2300.c */
427 int ast_2300_post(struct ast_device *ast);
428
429 /* ast_2500.c */
430 void ast_2500_patch_ahb(void __iomem *regs);
431 int ast_2500_post(struct ast_device *ast);
432
433 /* ast_2600.c */
434 int ast_2600_post(struct ast_device *ast);
435
436 /* ast post */
437 int ast_post_gpu(struct ast_device *ast);
438 u32 ast_mindwm(struct ast_device *ast, u32 r);
439 void ast_moutdwm(struct ast_device *ast, u32 r, u32 v);
440
441 int ast_vga_output_init(struct ast_device *ast);
442 int ast_sil164_output_init(struct ast_device *ast);
443
444 /* ast_cursor.c */
445 long ast_cursor_vram_offset(struct ast_device *ast);
446 int ast_cursor_plane_init(struct ast_device *ast);
447
448 /* ast dp501 */
449 bool ast_backup_fw(struct ast_device *ast, u8 *addr, u32 size);
450 void ast_init_3rdtx(struct ast_device *ast);
451 int ast_dp501_output_init(struct ast_device *ast);
452
453 /* aspeed DP */
454 int ast_dp_launch(struct ast_device *ast);
455 int ast_astdp_output_init(struct ast_device *ast);
456
457 /* ast_mode.c */
458 int ast_mode_config_init(struct ast_device *ast);
459 int ast_plane_init(struct drm_device *dev, struct ast_plane *ast_plane,
460 u64 offset, unsigned long size,
461 uint32_t possible_crtcs,
462 const struct drm_plane_funcs *funcs,
463 const uint32_t *formats, unsigned int format_count,
464 const uint64_t *format_modifiers,
465 enum drm_plane_type type);
466 void __iomem *ast_plane_vaddr(struct ast_plane *ast);
467
468 #endif
469