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Searched refs:Array (Results 1 – 15 of 15) sorted by relevance

/drivers/staging/rtl8723bs/hal/
A DHalHWImg8723B_BB.c216 u32 *Array = Array_MP_8723B_AGC_TAB; in ODM_ReadAndConfig_MP_8723B_AGC_TAB() local
219 u32 v1 = Array[i]; in ODM_ReadAndConfig_MP_8723B_AGC_TAB()
220 u32 v2 = Array[i+1]; in ODM_ReadAndConfig_MP_8723B_AGC_TAB()
475 u32 *Array = Array_MP_8723B_PHY_REG; in ODM_ReadAndConfig_MP_8723B_PHY_REG() local
478 u32 v1 = Array[i]; in ODM_ReadAndConfig_MP_8723B_PHY_REG()
479 u32 v2 = Array[i+1]; in ODM_ReadAndConfig_MP_8723B_PHY_REG()
544 u32 *Array = Array_MP_8723B_PHY_REG_PG; in ODM_ReadAndConfig_MP_8723B_PHY_REG_PG() local
550 u32 v1 = Array[i]; in ODM_ReadAndConfig_MP_8723B_PHY_REG_PG()
551 u32 v2 = Array[i+1]; in ODM_ReadAndConfig_MP_8723B_PHY_REG_PG()
552 u32 v3 = Array[i+2]; in ODM_ReadAndConfig_MP_8723B_PHY_REG_PG()
[all …]
A DHalHWImg8723B_RF.c217 u32 *Array = Array_MP_8723B_RadioA; in ODM_ReadAndConfig_MP_8723B_RadioA() local
220 u32 v1 = Array[i]; in ODM_ReadAndConfig_MP_8723B_RadioA()
221 u32 v2 = Array[i+1]; in ODM_ReadAndConfig_MP_8723B_RadioA()
534 u8 **Array = Array_MP_8723B_TXPWR_LMT; in ODM_ReadAndConfig_MP_8723B_TXPWR_LMT() local
537 u8 *regulation = Array[i]; in ODM_ReadAndConfig_MP_8723B_TXPWR_LMT()
538 u8 *bandwidth = Array[i+1]; in ODM_ReadAndConfig_MP_8723B_TXPWR_LMT()
539 u8 *rate = Array[i+2]; in ODM_ReadAndConfig_MP_8723B_TXPWR_LMT()
540 u8 *rfPath = Array[i+3]; in ODM_ReadAndConfig_MP_8723B_TXPWR_LMT()
541 u8 *chnl = Array[i+4]; in ODM_ReadAndConfig_MP_8723B_TXPWR_LMT()
542 u8 *val = Array[i+5]; in ODM_ReadAndConfig_MP_8723B_TXPWR_LMT()
A DHalHWImg8723B_MAC.c186 u32 *Array = Array_MP_8723B_MAC_REG; in ODM_ReadAndConfig_MP_8723B_MAC_REG() local
189 u32 v1 = Array[i]; in ODM_ReadAndConfig_MP_8723B_MAC_REG()
190 u32 v2 = Array[i+1]; in ODM_ReadAndConfig_MP_8723B_MAC_REG()
A Dodm_types.h47 …EXT_PAIR(v1, v2, i) do { if (i+2 >= ArrayLen) break; i += 2; v1 = Array[i]; v2 = Array[i+1]; } whi…
A Dhal_com.c886 u32 *Array = Array_kfreemap; in rtw_bb_rf_gain_offset() local
895 v1 = Array[i]; in rtw_bb_rf_gain_offset()
896 v2 = Array[i+1]; in rtw_bb_rf_gain_offset()
/drivers/mtd/nand/onenand/
A DKconfig47 One Block of the NAND Flash Array memory is reserved as
49 Also, 1st Block of NAND Flash Array can be used as OTP.
52 operations as any other NAND Flash Array memory block.
/drivers/eisa/
A Deisa.ids87 ALR8580 "Advanced Disk Array Caching EISA Controller"
233 CPQ4001 "Compaq 32-Bit Intelligent Drive Array Controller"
234 CPQ4002 "Compaq Intelligent Drive Array Controller-2"
236 CPQ4020 "Compaq SMART Array Controller"
237 CPQ4030 "Compaq SMART-2/E Array Controller"
477 DEL4001 "Dell Drive Array"
478 DEL4002 "Dell SCSI Array Controller"
1056 ISADF03 "Weitek Array Processor, Brd #3002-0046-01"
1102 MLX0070 "Mylex DAC960 EISA Disk Array Controller"
1103 MLX0071 "Mylex DAC960 EISA Disk Array Controller (3-channel)"
[all …]
/drivers/fpga/
A DKconfig174 Gate Array (FPGA) solutions which implement Device Feature List.
230 Field-Programmable Gate Array (FPGA) solutions which implement
/drivers/gpu/drm/msm/registers/
A Dgen_header.py280 class Array(object): class
675 self.current_array = Array(attrs, self.prefix(variant), variant, self.current_array, index_type)
/drivers/scsi/aic7xxx/
A Daic7xxx.reg1016 * Byte offset into the SCB Array and an optional bit to allow auto
1281 field ARRDONE 0x40 /* SCB Array prefetch done */
A Daic79xx.reg2894 * CMC SCB Array Count
/drivers/pinctrl/
A DKconfig293 Programmable IO Array (FPIOA) controller.
/drivers/scsi/
A DKconfig361 tristate "HP Smart Array SCSI driver"
366 This driver supports HP Smart Array Controllers (circa 2009).
368 driver. Anyone wishing to use HP Smart Array controllers who
/drivers/firmware/arm_scmi/vendors/imx/
A Dimx95.rst425 |uint32 extinfo[3] |Array of extended info words(e.g. fault pc) |
1595 |uint32 extinfo[8] |Array of extended info words |
/drivers/input/misc/
A DKconfig861 tristate "Windows-compatible SoC Button Array"

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