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Searched refs:BASE (Results 1 – 25 of 93) sorted by relevance

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/drivers/gpu/nova-core/
A Dfalcon.rs280 const BASE: usize; consts
416 .write(bar, E::BASE); in reset()
467 .write(bar, E::BASE); in dma_wr()
470 .write(bar, E::BASE); in dma_wr()
481 .write(bar, E::BASE); in dma_wr()
484 .write(bar, E::BASE); in dma_wr()
485 cmd.write(bar, E::BASE); in dma_wr()
520 .write(bar, E::BASE); in dma_load()
541 .write(bar, E::BASE); in boot()
547 .write(bar, E::BASE); in boot()
[all …]
/drivers/gpu/nova-core/falcon/hal/
A Dga102.rs19 let bcr_ctrl = regs::NV_PRISCV_RISCV_BCR_CTRL::read(bar, E::BASE); in select_core_ga102()
23 .write(bar, E::BASE); in select_core_ga102()
27 let r = regs::NV_PRISCV_RISCV_BCR_CTRL::read(bar, E::BASE); in select_core_ga102()
79 .write(bar, E::BASE); in program_brom_ga102()
82 .write(bar, E::BASE); in program_brom_ga102()
85 .write(bar, E::BASE); in program_brom_ga102()
88 .write(bar, E::BASE); in program_brom_ga102()
/drivers/media/pci/cobalt/
A Dcobalt-omnitek.c42 #define BASE (cobalt->bar0) macro
43 #define CAPABILITY_HEADER (BASE)
44 #define CAPABILITY_REGISTER (BASE + 0x04)
47 #define INTERRUPT_STATUS (BASE + 0x08)
48 #define PCI(c) (BASE + 0x40 + ((c) * 0x40))
49 #define SIZE(c) (BASE + 0x58 + ((c) * 0x40))
50 #define DESCRIPTOR(c) (BASE + 0x50 + ((c) * 0x40))
51 #define CS_REG(c) (BASE + 0x60 + ((c) * 0x40))
52 #define BYTES_TRANSFERRED(c) (BASE + 0x64 + ((c) * 0x40))
/drivers/gpu/nova-core/falcon/
A Dgsp.rs13 const BASE: usize = 0x00110000; consts
22 .write(bar, Gsp::BASE); in clear_swgen0_intr()
/drivers/gpu/drm/amd/display/dc/gpio/dce120/
A Dhw_factory_dce120.c57 #define BASE(seg) \ macro
61 BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
64 BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
A Dhw_translate_dce120.c48 #define BASE(seg) \ macro
52 BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
55 BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
/drivers/ps3/
A Dps3av_cmd.c489 #define BASE PS3AV_CMD_AUDIO_FS_44K macro
493 [PS3AV_CMD_AUDIO_FS_44K-BASE] = { 6272, 6272, 17836, 17836, 8918 },
494 [PS3AV_CMD_AUDIO_FS_48K-BASE] = { 6144, 6144, 11648, 11648, 5824 },
495 [PS3AV_CMD_AUDIO_FS_88K-BASE] = { 12544, 12544, 35672, 35672, 17836 },
496 [PS3AV_CMD_AUDIO_FS_96K-BASE] = { 12288, 12288, 23296, 23296, 11648 },
497 [PS3AV_CMD_AUDIO_FS_176K-BASE] = { 25088, 25088, 71344, 71344, 35672 },
498 [PS3AV_CMD_AUDIO_FS_192K-BASE] = { 24576, 24576, 46592, 46592, 23296 }
540 ns_val = ps3av_ns_table[PS3AV_CMD_AUDIO_FS_44K-BASE][d]; in ps3av_cnv_ns()
547 #undef BASE
/drivers/gpu/drm/amd/display/dc/gpio/dcn10/
A Dhw_factory_dcn10.c54 #define BASE(seg) \ macro
58 BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
61 BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
A Dhw_translate_dcn10.c48 #define BASE(seg) \ macro
52 BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
55 BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
/drivers/gpu/drm/amd/display/dc/gpio/dcn21/
A Dhw_factory_dcn21.c53 #define BASE(seg) BASE_INNER(seg) macro
58 BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
64 BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
/drivers/media/tuners/
A Dxc4000.c552 if (type & BASE) in dump_firm_type_and_int_freq()
960 if (priv->cur_fw.type & BASE) { in check_firmware()
975 rc = load_firmware(fe, BASE, &std0); in check_firmware()
984 rc = load_firmware(fe, BASE | INIT1, &std0); in check_firmware()
986 rc = load_firmware(fe, BASE | INIT1, &std0); in check_firmware()
998 if (priv->cur_fw.type == (BASE | new_fw.type) && in check_firmware()
1070 priv->cur_fw.type |= BASE; in check_firmware()
1523 & (BASE | FM | DTV6 | DTV7 | DTV78 | DTV8)) == BASE) { in xc4000_get_frequency()
1556 if (priv->cur_fw.type & BASE) in xc4000_get_status()
1583 (priv->cur_fw.type & BASE) != 0) { in xc4000_sleep()
[all …]
A Dxc2028-types.h14 #define BASE (1<<0) macro
15 #define BASE_TYPES (BASE|F8MHZ|MTS|FM|INPUT1|INPUT2|INIT1)
/drivers/gpu/drm/amd/display/dc/resource/dcn35/
A Ddcn35_resource.c129 #define BASE(seg) BASE_INNER(seg) macro
132 REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
136 REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
142 REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
150 REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
161 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
165 REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
169 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
181 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
548 .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \
[all …]
/drivers/gpu/drm/amd/display/dc/resource/dcn351/
A Ddcn351_resource.c109 #define BASE(seg) BASE_INNER(seg) macro
112 REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
116 REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
122 REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
130 REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
141 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
145 REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
149 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
161 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
528 .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \
[all …]
/drivers/gpu/drm/amd/display/dc/resource/dcn36/
A Ddcn36_resource.c114 #define BASE(seg) BASE_INNER(seg) macro
117 REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
121 REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
127 REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
135 REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
146 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
150 REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
154 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
166 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
529 .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \
[all …]
/drivers/gpu/drm/amd/display/dc/gpio/dcn20/
A Dhw_factory_dcn20.c55 #define BASE(seg) BASE_INNER(seg) macro
60 BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
66 BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
/drivers/gpu/drm/amd/display/dc/gpio/dcn30/
A Dhw_factory_dcn30.c62 #define BASE(seg) BASE_INNER(seg) macro
67 BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
73 BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
/drivers/gpu/drm/amd/display/dc/gpio/dcn315/
A Dhw_factory_dcn315.c59 #define BASE(seg) BASE_INNER(seg) macro
64 BASE(reg ## reg_name ## _BASE_IDX) + reg ## reg_name
70 BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
/drivers/gpu/drm/amd/display/dc/gpio/dcn32/
A Dhw_factory_dcn32.c55 #define BASE(seg) BASE_INNER(seg) macro
60 BASE(reg ## reg_name ## _BASE_IDX) + reg ## reg_name
66 BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
/drivers/gpu/drm/amd/display/dc/gpio/dcn401/
A Dhw_factory_dcn401.c35 #define BASE(seg) BASE_INNER(seg) macro
40 BASE(reg ## reg_name ## _BASE_IDX) + reg ## reg_name
46 BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/
A Ddcn351_clk_mgr.c101 #define BASE(seg) BASE_INNER(seg) macro
104 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
/drivers/gpu/drm/amd/display/dc/resource/dcn321/
A Ddcn321_resource.c115 #define BASE(seg) BASE_INNER(seg) macro
118 REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
121 REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
127 REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
131 REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
135 REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
146 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
149 REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
153 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
165 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
[all …]
/drivers/gpu/drm/amd/display/dc/dcn10/
A Ddcn10_dwb.h31 #define BASE(seg) \ macro
35 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
39 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
44 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
/drivers/gpu/drm/amd/display/dc/resource/dcn401/
A Ddcn401_resource.c96 #define BASE(seg) BASE_INNER(seg) macro
99 REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
102 REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
108 REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
119 REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## reg_name ## _BASE_IDX) + \
122 REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
133 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
136 REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
140 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
152 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
[all …]
/drivers/net/phy/
A DKconfig125 - ADIN1100 - Robust,Industrial, Low Power 10BASE-T1L Ethernet PHY
265 Support for the Marvell 88Q2XXX 100/1000BASE-T1 Automotive Ethernet
304 tristate "Microchip 10BASE-T1S Ethernet PHYs"
347 tristate "NXP 100BASE-TX PHYs"
349 Support the 100BASE-TX PHY integrated on the SJA1110 automotive
367 tristate "Onsemi 10BASE-T1S Ethernet PHY"
369 Adds support for the onsemi 10BASE-T1S Ethernet PHY.
370 Currently supports the NCN26000 10BASE-T1S Industrial PHY

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