| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/ |
| A D | dcn314_smu.c | 45 #ifdef BASE_INNER
46 #undef BASE_INNER
49 #define BASE_INNER(seg) MP1_BASE__INST0_SEG ## seg macro
51 #define BASE(seg) BASE_INNER(seg)
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| /drivers/gpu/drm/amd/display/dc/irq/dcn201/ |
| A D | irq_service_dcn201.c | 112 #undef BASE_INNER
113 #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg macro
115 #define BASE(seg) BASE_INNER(seg)
119 BASE_INNER(seg)
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| /drivers/gpu/drm/amd/display/dc/gpio/dcn21/ |
| A D | hw_factory_dcn21.c | 50 #undef BASE_INNER
51 #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg macro
53 #define BASE(seg) BASE_INNER(seg)
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| A D | hw_translate_dcn21.c | 49 #undef BASE_INNER
50 #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg macro
52 #define BASE(seg) BASE_INNER(seg)
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| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/ |
| A D | dcn35_smu.c | 45 #ifdef BASE_INNER
46 #undef BASE_INNER
49 #define BASE_INNER(seg) MP1_BASE__INST0_SEG ## seg macro
51 #define BASE(seg) BASE_INNER(seg)
|
| A D | dcn351_clk_mgr.c | 99 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg macro
101 #define BASE(seg) BASE_INNER(seg)
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| /drivers/gpu/drm/amd/display/dc/gpio/dcn20/ |
| A D | hw_factory_dcn20.c | 52 #undef BASE_INNER
53 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg macro
55 #define BASE(seg) BASE_INNER(seg)
|
| A D | hw_translate_dcn20.c | 49 #undef BASE_INNER
50 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg macro
52 #define BASE(seg) BASE_INNER(seg)
|
| /drivers/gpu/drm/amd/display/dc/gpio/dcn32/ |
| A D | hw_translate_dcn32.c | 47 #undef BASE_INNER
48 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg macro
50 #define BASE(seg) BASE_INNER(seg)
|
| A D | hw_factory_dcn32.c | 52 #undef BASE_INNER
53 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg macro
55 #define BASE(seg) BASE_INNER(seg)
|
| /drivers/gpu/drm/amd/display/dc/gpio/dcn401/ |
| A D | hw_translate_dcn401.c | 22 #undef BASE_INNER
23 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg macro
25 #define BASE(seg) BASE_INNER(seg)
|
| A D | hw_factory_dcn401.c | 32 #undef BASE_INNER
33 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg macro
35 #define BASE(seg) BASE_INNER(seg)
|
| /drivers/gpu/drm/amd/display/dc/gpio/dcn30/ |
| A D | hw_factory_dcn30.c | 59 #undef BASE_INNER
60 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg macro
62 #define BASE(seg) BASE_INNER(seg)
|
| A D | hw_translate_dcn30.c | 54 #undef BASE_INNER
55 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg macro
57 #define BASE(seg) BASE_INNER(seg)
|
| /drivers/gpu/drm/amd/display/dc/gpio/dcn315/ |
| A D | hw_factory_dcn315.c | 56 #undef BASE_INNER
57 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg macro
59 #define BASE(seg) BASE_INNER(seg)
|
| A D | hw_translate_dcn315.c | 49 #undef BASE_INNER
50 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg macro
52 #define BASE(seg) BASE_INNER(seg)
|
| /drivers/gpu/drm/amd/display/dc/irq/dcn303/ |
| A D | irq_service_dcn303.c | 110 #undef BASE_INNER
111 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg macro
114 #define BASE(seg) BASE_INNER(seg)
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| /drivers/gpu/drm/amd/display/dc/irq/dcn20/ |
| A D | irq_service_dcn20.c | 163 #undef BASE_INNER
164 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg macro
168 BASE_INNER(seg)
|
| /drivers/gpu/drm/amd/display/dc/gpio/dce120/ |
| A D | hw_factory_dce120.c | 53 #define BASE_INNER(seg) \ macro
58 BASE_INNER(seg)
|
| /drivers/gpu/drm/amd/display/dc/irq/dcn21/ |
| A D | irq_service_dcn21.c | 170 #undef BASE_INNER
171 #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg macro
175 BASE_INNER(seg)
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| /drivers/gpu/drm/amd/display/dc/irq/dcn31/ |
| A D | irq_service_dcn31.c | 166 #undef BASE_INNER
167 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg macro
171 BASE_INNER(seg)
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| /drivers/gpu/drm/amd/display/dc/irq/dcn314/ |
| A D | irq_service_dcn314.c | 168 #undef BASE_INNER
169 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg macro
173 BASE_INNER(seg)
|
| /drivers/gpu/drm/amd/display/dc/irq/dcn315/ |
| A D | irq_service_dcn315.c | 173 #undef BASE_INNER
174 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg macro
178 BASE_INNER(seg)
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| /drivers/gpu/drm/amd/display/dc/irq/dcn30/ |
| A D | irq_service_dcn30.c | 177 #undef BASE_INNER
178 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg macro
182 BASE_INNER(seg)
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| /drivers/gpu/drm/amd/display/dc/irq/dcn302/ |
| A D | irq_service_dcn302.c | 164 #undef BASE_INNER
165 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg macro
168 #define BASE(seg) BASE_INNER(seg)
|