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/drivers/platform/x86/intel/pmc/
A Dmtl.c30 {"PMC", BIT(0)},
31 {"OPI", BIT(1)},
32 {"SPI", BIT(2)},
33 {"XHCI", BIT(3)},
34 {"SPA", BIT(4)},
35 {"SPB", BIT(5)},
36 {"SPC", BIT(6)},
37 {"GBE", BIT(7)},
39 {"SATA", BIT(0)},
40 {"DSP0", BIT(1)},
[all …]
A Dlnl.c393 {"XHCI", BIT(3)},
394 {"SPA", BIT(4)},
395 {"SPB", BIT(5)},
397 {"GBE", BIT(7)},
403 {"ESE", BIT(3)},
406 {"LPSS", BIT(6)},
407 {"LPC", BIT(7)},
409 {"SMB", BIT(0)},
410 {"ISH", BIT(1)},
415 {"FUSE", BIT(6)},
[all …]
A Dptl.c35 {"NPK_0", BIT(3)},
41 {"PSF0", BIT(0)},
45 {"KVMCC", BIT(4)},
46 {"PMT", BIT(5)},
47 {"CLINK", BIT(6)},
48 {"PTIO", BIT(7)},
52 {"SMT1", BIT(2)},
54 {"SMS2", BIT(4)},
55 {"SMS1", BIT(5)},
60 {"ESE", BIT(1)},
[all …]
A Darl.c63 {"AON2_OFF_STS", BIT(0)},
64 {"AON3_OFF_STS", BIT(1)},
65 {"AON4_OFF_STS", BIT(2)},
66 {"AON5_OFF_STS", BIT(3)},
242 {"RSVD64", BIT(0)},
243 {"RSVD65", BIT(1)},
244 {"RSVD66", BIT(2)},
245 {"RSVD67", BIT(3)},
246 {"RSVD68", BIT(4)},
247 {"GBETSN", BIT(5)},
[all …]
A Dadl.c16 {"XHCI", BIT(3)},
17 {"SPA", BIT(4)},
18 {"SPB", BIT(5)},
19 {"SPC", BIT(6)},
20 {"GBE", BIT(7)},
22 {"SATA", BIT(0)},
27 {"SPD", BIT(5)},
28 {"LPSS", BIT(6)},
30 {"SMB", BIT(0)},
31 {"ISH", BIT(1)},
[all …]
A Dtgl.c22 {"PSF9", BIT(0)},
23 {"RES_66", BIT(1)},
24 {"RES_67", BIT(2)},
25 {"RES_68", BIT(3)},
26 {"RES_69", BIT(4)},
27 {"RES_70", BIT(5)},
28 {"TBTLSX", BIT(6)},
63 {"OTG_PG_STS", BIT(5)},
64 {"SPA_PG_STS", BIT(6)},
65 {"SPB_PG_STS", BIT(7)},
[all …]
A Dcnp.c43 {"SBR8", BIT(7)},
78 {"SPF", BIT(6)},
86 {"PSF6", BIT(5)},
87 {"PSF7", BIT(6)},
88 {"PSF8", BIT(7)},
103 {"OTG_D3", BIT(1)},
104 {"XHCI_D3", BIT(2)},
105 {"LPIO_D3", BIT(3)},
106 {"SDX_D3", BIT(4)},
107 {"SATA_D3", BIT(5)},
[all …]
/drivers/crypto/intel/qat/qat_common/
A Dadf_gen4_ras.h72 (BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(5) | \
74 BIT(14) | BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19) | \
75 BIT(20) | BIT(21) | BIT(22) | BIT(23) | BIT(24) | BIT(25) | \
119 (BIT(0) | BIT(1) | BIT(2) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | \
120 BIT(8) | BIT(9) | BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14))
162 (BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | \
163 BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) | BIT(12) | BIT(13) | \
195 (BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | \
290 (BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(5) | BIT(6) | BIT(7) | \
291 BIT(8) | BIT(9) | BIT(10) | BIT(11) | BIT(13) | BIT(14) | BIT(15))
[all …]
A Dadf_gen6_ras.h98 (BIT(0) | BIT(1) | BIT(2) | BIT(4) | BIT(5) | BIT(6) | \
99 BIT(7) | BIT(8) | BIT(18) | BIT(19) | BIT(20) | BIT(21) | \
100 BIT(22) | BIT(23) | BIT(24) | BIT(25) | BIT(26) | BIT(27) | \
143 (BIT(0) | BIT(1) | BIT(2) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | \
144 BIT(8) | BIT(9) | BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14))
164 BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10))
186 (BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | \
187 BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) | BIT(12) | BIT(13) | \
188 BIT(14) | BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(20) | \
219 (BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | \
[all …]
/drivers/clk/stm32/
A Dstm32mp13_rcc.h339 #define RCC_BDCR_LSEON BIT(0)
340 #define RCC_BDCR_LSEBYP BIT(1)
341 #define RCC_BDCR_LSERDY BIT(2)
342 #define RCC_BDCR_DIGBYP BIT(3)
344 #define RCC_BDCR_LSECSSON BIT(8)
345 #define RCC_BDCR_LSECSSD BIT(9)
347 #define RCC_BDCR_RTCCKEN BIT(20)
442 #define RCC_PLL1CR_PLLON BIT(0)
478 #define RCC_PLL2CR_PLLON BIT(0)
514 #define RCC_PLL3CR_PLLON BIT(0)
[all …]
/drivers/net/wireless/realtek/rtw89/
A Dreg.h9 #define B_AX_AUTOLOAD_SUS BIT(5)
15 #define B_AX_ISO_EB2CORE BIT(8)
19 #define B_AX_FEN_BBRSTB BIT(0)
22 #define B_AX_SOP_ASWRM BIT(31)
28 #define B_AX_EN_WLON BIT(16)
56 #define B_AX_EF_RDT BIT(27)
60 #define B_AX_EF_POR BIT(10)
65 #define B_AX_EF_RDY BIT(29)
86 #define B_AX_ENHTP BIT(14)
88 #define B_AX_ENSIC BIT(12)
[all …]
A Dpci.h18 #define BAC_OOBS_SEL BIT(4)
20 #define B_BAC_EQ_SEL BIT(5)
24 #define B_PCIE_BIT_PSAVE BIT(15)
26 #define OFFSET_CAL_MODE BIT(13)
27 #define BAC_RX_TEST_EN BIT(6)
37 #define B_PCIE_BIT_RD_SEL BIT(2)
55 #define B_AX_CALIB_EN BIT(13)
60 #define B_AX_DBI_RFLAG BIT(17)
61 #define B_AX_DBI_WFLAG BIT(16)
89 #define B_AX_CLK_REQ_N BIT(1)
[all …]
/drivers/gpu/drm/bridge/
A Dsil-sii8620.h46 #define BIT_DPD_PWRON_PLL BIT(7)
47 #define BIT_DPD_PDNTX12 BIT(6)
48 #define BIT_DPD_PDNRX12 BIT(5)
49 #define BIT_DPD_OSC_EN BIT(4)
50 #define BIT_DPD_PWRON_HSIC BIT(3)
51 #define BIT_DPD_PDIDCK_N BIT(2)
60 #define BIT_DCTL_TRANSCODE BIT(3)
149 #define BIT_DDC_CMD_DONE BIT(3)
219 #define BIT_BIST_TRANS BIT(2)
220 #define BIT_BIST_RESET BIT(1)
[all …]
/drivers/net/ethernet/freescale/dpaa2/
A Ddpkg.h64 #define NH_FLD_ETH_DA BIT(0)
65 #define NH_FLD_ETH_SA BIT(1)
67 #define NH_FLD_ETH_TYPE BIT(3)
73 #define NH_FLD_VLAN_VPRI BIT(0)
85 #define NH_FLD_IP_VER BIT(0)
86 #define NH_FLD_IP_DSCP BIT(2)
87 #define NH_FLD_IP_ECN BIT(3)
89 #define NH_FLD_IP_SRC BIT(5)
90 #define NH_FLD_IP_DST BIT(6)
92 #define NH_FLD_IP_ID BIT(8)
[all …]
/drivers/net/wireless/realtek/rtl8xxxu/
A Dregs.h124 #define EFUSE_CELL_SEL (BIT(8) | BIT(9))
309 #define HPON_FSM_BONDING_MASK (BIT(22) | BIT(23))
324 #define SYS_CFG_CHIP_VER (BIT(12) | BIT(13) | BIT(14) | BIT(15))
327 #define SYS_CFG_VENDOR_EXT_MASK (BIT(18) | BIT(19))
345 #define GPIO_EFS_HCI_SEL (BIT(0) | BIT(1))
346 #define GPIO_PAD_HCI_SEL (BIT(2) | BIT(3))
347 #define GPIO_HCI_SEL (BIT(4) | BIT(5))
364 #define GPIO_RF_RL_ID (BIT(31) | BIT(30) | BIT(29) | BIT(28))
817 #define WMAC_TRXPTCL_CTL_BW_MASK (BIT(7) | BIT(8))
1023 #define CCK0_AFE_RX_ANT_D (BIT(26) | BIT(27))
[all …]
/drivers/staging/sm750fb/
A Dddk750_reg.h7 #define DE_STATE1_DE_ABORT BIT(0)
10 #define DE_STATE2_DE_FIFO_EMPTY BIT(3)
11 #define DE_STATE2_DE_STATUS_BUSY BIT(2)
12 #define DE_STATE2_DE_MEM_FIFO_EMPTY BIT(1)
20 #define SYSTEM_CTRL_PCI_BURST BIT(29)
21 #define SYSTEM_CTRL_PCI_MASTER BIT(25)
22 #define SYSTEM_CTRL_LATENCY_TIMER_OFF BIT(24)
23 #define SYSTEM_CTRL_DE_FIFO_EMPTY BIT(23)
24 #define SYSTEM_CTRL_DE_STATUS_BUSY BIT(22)
25 #define SYSTEM_CTRL_DE_MEM_FIFO_EMPTY BIT(21)
[all …]
/drivers/gpu/drm/mcde/
A Dmcde_dsi_regs.h8 #define DSI_MCTL_MAIN_DATA_CTL_LINK_EN BIT(0)
9 #define DSI_MCTL_MAIN_DATA_CTL_IF1_MODE BIT(1)
10 #define DSI_MCTL_MAIN_DATA_CTL_VID_EN BIT(2)
11 #define DSI_MCTL_MAIN_DATA_CTL_TVG_SEL BIT(3)
66 #define DSI_MCTL_MAIN_EN_DAT1_EN BIT(4)
67 #define DSI_MCTL_MAIN_EN_DAT2_EN BIT(5)
71 #define DSI_MCTL_MAIN_EN_IF1_EN BIT(9)
72 #define DSI_MCTL_MAIN_EN_IF2_EN BIT(10)
182 #define DSI_VID_MAIN_CTL_VID_PIXEL_MODE_24BITS (BIT(12) | BIT(13))
189 #define DSI_VID_MAIN_CTL_REG_BLKLINE_MODE_LP_1 (BIT(17) | BIT(18))
[all …]
/drivers/usb/dwc2/
A Dhw.h15 #define GOTGCTL_CHIRPEN BIT(27)
19 #define GOTGCTL_OTGVER BIT(20)
20 #define GOTGCTL_BSESVLD BIT(19)
21 #define GOTGCTL_ASESVLD BIT(18)
23 #define GOTGCTL_CONID_B BIT(16)
27 #define GOTGCTL_HNPREQ BIT(9)
29 #define GOTGCTL_BVALOVAL BIT(7)
30 #define GOTGCTL_BVALOEN BIT(6)
31 #define GOTGCTL_AVALOVAL BIT(5)
35 #define GOTGCTL_SESREQ BIT(1)
[all …]
/drivers/net/dsa/microchip/
A Dksz9477_reg.h45 #define SW_AVB_ABLE BIT(4)
63 #define SW_QW_ABLE BIT(5)
69 #define LUE_INT BIT(31)
70 #define TRIG_TS_INT BIT(30)
112 #define SW_IBA_REQ BIT(31)
149 #define SW_RESET BIT(1)
388 #define ALU_START BIT(7)
389 #define ALU_VALID BIT(6)
572 #define GPIO_IN BIT(7)
573 #define GPIO_OUT BIT(6)
[all …]
/drivers/comedi/drivers/
A Dni_stc.h26 #define NISTC_INTA_ACK_G0_TC BIT(14)
27 #define NISTC_INTA_ACK_AI_ERR BIT(13)
144 #define NISTC_DIO_SDIN BIT(4)
145 #define NISTC_DIO_SDOUT BIT(0)
256 #define NISTC_RTSI_TRIG_DIR(_c, _m) ((_m) ? BIT(8 + (_c)) : BIT(7 + (_c)))
360 #define NISTC_RESET_G1 BIT(3)
361 #define NISTC_RESET_G0 BIT(2)
362 #define NISTC_RESET_AO BIT(1)
363 #define NISTC_RESET_AI BIT(0)
671 #define CS5529_CMD_CB BIT(7)
[all …]
/drivers/net/wireless/realtek/rtlwifi/rtl8192d/
A Dreg.h71 #define MAC0_ON BIT(7)
72 #define MAC1_ON BIT(0)
73 #define MAC0_READY BIT(0)
74 #define MAC1_READY BIT(0)
368 #define RRSR_1M BIT(0)
369 #define RRSR_2M BIT(1)
371 #define RRSR_11M BIT(3)
372 #define RRSR_6M BIT(4)
373 #define RRSR_9M BIT(5)
1022 #define ACRC BIT(8)
[all …]
/drivers/net/ethernet/mediatek/
A Dmtk_wed_regs.h7 #define MTK_WFDMA_DESC_CTRL_TO_HOST BIT(8)
10 #define MTK_WDMA_DESC_CTRL_LAST_SEG1 BIT(15)
11 #define MTK_WDMA_DESC_CTRL_BURST BIT(16)
14 #define MTK_WDMA_DESC_CTRL_DMA_DONE BIT(31)
29 #define MTK_WED_RESET_TX_BM BIT(0)
30 #define MTK_WED_RESET_RX_BM BIT(1)
31 #define MTK_WED_RESET_RX_PG_BM BIT(2)
45 #define MTK_WED_RESET_TX_AMSDU BIT(22)
46 #define MTK_WED_RESET_WED BIT(31)
518 #define MTK_WED_RTQM_BUSY BIT(1)
[all …]
/drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/
A Dsun8i_a83t_mipi_csi2_reg.h14 #define SUN8I_A83T_MIPI_CSI2_CTRL_RESET_N BIT(31)
24 #define SUN8I_A83T_MIPI_CSI2_INT_STA0_ECC_ERR_DBL BIT(28)
37 #define SUN8I_A83T_MIPI_CSI2_INT_STA0_CRC_ERR_VC3 BIT(15)
70 #define SUN8I_A83T_MIPI_CSI2_INT_STA1_SOT_ERR_3 BIT(7)
71 #define SUN8I_A83T_MIPI_CSI2_INT_STA1_SOT_ERR_2 BIT(6)
72 #define SUN8I_A83T_MIPI_CSI2_INT_STA1_SOT_ERR_1 BIT(5)
73 #define SUN8I_A83T_MIPI_CSI2_INT_STA1_SOT_ERR_0 BIT(4)
128 #define SUN8I_A83T_MIPI_CSI2_CFG_SYNC_EN BIT(31)
130 #define SUN8I_A83T_MIPI_CSI2_CFG_UNPKT_EN BIT(28)
132 #define SUN8I_A83T_MIPI_CSI2_CFG_YC_SWAB BIT(26)
[all …]
/drivers/net/ethernet/asix/
A Dax88796c_main.h121 #define AX_FC_RX BIT(0)
122 #define AX_FC_TX BIT(1)
159 #define FER_DCRC BIT(1)
160 #define FER_RH3M BIT(2)
171 #define ISR_MDQ BIT(4)
172 #define ISR_TXT BIT(5)
175 #define ISR_LINK BIT(9)
178 #define IMR_MDQ BIT(4)
179 #define IMR_TXT BIT(5)
182 #define IMR_LINK BIT(9)
[all …]
/drivers/scsi/
A Dnsp32.h239 # define SD0 BIT(0)
240 # define SD1 BIT(1)
241 # define SD2 BIT(2)
242 # define SD3 BIT(3)
243 # define SD4 BIT(4)
244 # define SD5 BIT(5)
245 # define SD6 BIT(6)
246 # define SD7 BIT(7)
282 # define MSGOUT_COUNT_MASK (BIT(0)|BIT(1))
392 # define SCL BIT(0)
[all …]

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