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Searched refs:BITS (Results 1 – 21 of 21) sorted by relevance

/drivers/mfd/
A Ddb8500-prcmu-regs.h120 #define PRCM_PLL_FREQ_D_MASK BITS(0, 7)
122 #define PRCM_PLL_FREQ_N_MASK BITS(8, 13)
124 #define PRCM_PLL_FREQ_R_MASK BITS(16, 18)
166 #define PRCM_CLKOCR_CLKOUT0_MASK BITS(0, 13)
168 #define PRCM_CLKOCR_CLKOUT1_MASK BITS(16, 29)
188 #define PRCM_TCR_TENSEL_MASK BITS(0, 7)
193 #define PRCM_CLKOCR_CLKODIV0_MASK BITS(0, 5)
195 #define PRCM_CLKOCR_CLKOSEL0_MASK BITS(6, 8)
197 #define PRCM_CLKOCR_CLKODIV1_MASK BITS(16, 21)
199 #define PRCM_CLKOCR_CLKOSEL1_MASK BITS(22, 24)
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/drivers/scsi/
A Daha152x.h291 #define SETBITS(PORT, BITS) outb( (inb(PORT) | (BITS)), (PORT) ) argument
292 #define CLRBITS(PORT, BITS) outb( (inb(PORT) & ~(BITS)), (PORT) ) argument
293 #define TESTHI(PORT, BITS) ((inb(PORT) & (BITS)) == (BITS)) argument
294 #define TESTLO(PORT, BITS) ((inb(PORT) & (BITS)) == 0) argument
A Dscsi_logging.h44 #define SCSI_LOG_LEVEL(SHIFT, BITS) \ argument
45 ((scsi_logging_level >> (SHIFT)) & ((1 << (BITS)) - 1))
47 #define SCSI_CHECK_LOGGING(SHIFT, BITS, LEVEL, CMD) \ argument
49 if (unlikely((SCSI_LOG_LEVEL(SHIFT, BITS)) > (LEVEL))) \
55 #define SCSI_LOG_LEVEL(SHIFT, BITS) 0 argument
56 #define SCSI_CHECK_LOGGING(SHIFT, BITS, LEVEL, CMD) do { } while (0) argument
/drivers/message/fusion/
A Dmptdebug.h69 #define MPT_CHECK_LOGGING(IOC, CMD, BITS) \ argument
71 if (IOC->debug_level & BITS) \
75 #define MPT_CHECK_LOGGING(IOC, CMD, BITS) \ argument
/drivers/scsi/mpt3sas/
A Dmpt3sas_debug.h71 #define MPT_CHECK_LOGGING(IOC, CMD, BITS) \ argument
73 if (IOC->logging_level & BITS) \
/drivers/gpu/drm/nouveau/
A Dnouveau_connector.h84 NVDEF(NV507D, HEAD_SET_DITHER_CONTROL, BITS, DITHER_TO_6_BITS),
86 NVDEF(NV507D, HEAD_SET_DITHER_CONTROL, BITS, DITHER_TO_8_BITS),
/drivers/media/platform/mediatek/mdp/
A Dmtk_mdp_regs.c14 #define MDP_COLORFMT_PACK(VIDEO, PLANE, COPLANE, HF, VF, BITS, GROUP, SWAP, ID)\ argument
16 ((HF) << 20) | ((VF) << 18) | ((BITS) << 8) | ((GROUP) << 6) |\
/drivers/firmware/efi/libstub/
A DMakefile14 cflags-$(CONFIG_X86) += -m$(BITS) -D__KERNEL__ -std=gnu11 \
148 STUBCOPY_RELOC-$(CONFIG_RISCV) := -E R_RISCV_HI20\|R_RISCV_$(BITS)\|R_RISCV_RELAX
/drivers/input/keyboard/
A Dlkkbd.c251 #define CHECK_LED(LK, VAR_ON, VAR_OFF, LED, BITS) do { \ argument
253 VAR_ON |= BITS; \
255 VAR_OFF |= BITS; \
/drivers/gpu/nova-core/fb/hal/
A Dtu102.rs18 if addr >> (u32::BITS + FLUSH_SYSMEM_ADDR_SHIFT) == 0 { in write_sysmem_flush_page_gm107()
/drivers/net/wireless/intel/iwlwifi/fw/api/
A Dcoex.h14 #define BITS(nb) (BIT(nb) - 1) macro
/drivers/media/platform/mediatek/mdp3/
A Dmtk-mdp3-regs.h21 #define MDP_COLOR(COMPRESS, PACKED, LOOSE, VIDEO, PLANE, HF, VF, BITS, GROUP, SWAP, ID)\ argument
23 ((PLANE) << 21) | ((HF) << 19) | ((VF) << 18) | ((BITS) << 8) |\
/drivers/gpu/nova-core/falcon/hal/
A Dga102.rs73 Ok(u32::BITS - reg_fuse_version.leading_zeros()) in signature_reg_fuse_version_ga102()
/drivers/gpu/drm/nouveau/dispnv50/
A Dhead917d.c42 NVVAL(NV917D, HEAD_SET_DITHER_CONTROL, BITS, asyh->dither.bits) | in head917d_dither()
A Dheadca7d.c102 NVVAL(NVCA7D, HEAD_SET_DITHER_CONTROL, BITS, asyh->dither.bits) | in headca7d_dither()
A Dheadc37d.c97 NVVAL(NVC37D, HEAD_SET_DITHER_CONTROL, BITS, asyh->dither.bits) | in headc37d_dither()
A Dhead507d.c60 NVVAL(NV507D, HEAD_SET_DITHER_CONTROL, BITS, asyh->dither.bits) | in head507d_dither()
A Dhead907d.c89 NVVAL(NV907D, HEAD_SET_DITHER_CONTROL, BITS, asyh->dither.bits) | in head907d_dither()
A Dhead.c116 asyh->dither.bits = NVVAL_GET(mode, NV507D, HEAD_SET_DITHER_CONTROL, BITS); in nv50_head_atomic_check_dither()
/drivers/net/ethernet/sun/
A Dniu.c150 #define niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \ argument
152 __niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
189 #define niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \ argument
191 __niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
209 #define niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY) \ argument
211 __niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY); \
229 #define niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \ argument
231 __niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
/drivers/spi/
A Dspi-atmel.c1291 csr = SPI_BF(BITS, bits - 8); in atmel_spi_setup()

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