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Searched refs:BLKADDR_CPT0 (Results 1 – 10 of 10) sorted by relevance

/drivers/crypto/marvell/octeontx2/
A Dotx2_cpt_devlink.c43 BLKADDR_CPT0); in otx2_cpt_dl_t106_mode_get()
63 &reg_val, BLKADDR_CPT0); in otx2_cpt_dl_t106_mode_set()
67 CPT_AF_CTL, reg_val, BLKADDR_CPT0); in otx2_cpt_dl_t106_mode_set()
A Dotx2_cptpf_ucode.c217 return cptx_set_ucode_base(eng_grp, cptpf, BLKADDR_CPT0); in cpt_set_ucode_base()
304 BLKADDR_CPT0); in cpt_detach_and_disable_cores()
363 return cptx_attach_and_enable_cores(eng_grp, cptpf, bmap, BLKADDR_CPT0); in cpt_attach_and_enable_cores()
1241 BLKADDR_CPT0); in otx2_cpt_create_eng_grps()
1249 reg_val, BLKADDR_CPT0); in otx2_cpt_create_eng_grps()
1256 CTX_FLUSH_TIMER_CNT, BLKADDR_CPT0); in otx2_cpt_create_eng_grps()
1266 &reg_val, BLKADDR_CPT0); in otx2_cpt_create_eng_grps()
1268 reg_val | BIT_ULL(24), BLKADDR_CPT0); in otx2_cpt_create_eng_grps()
1350 return cptx_disable_all_cores(cptpf, total_cores, BLKADDR_CPT0); in otx2_cpt_disable_all_cores()
A Dotx2_cptpf_main.c602 BLKADDR_CPT0); in cptpf_get_rid()
631 BLKADDR_CPT0); in cptpf_device_init()
643 &cptpf->afpf_mbox, BLKADDR_CPT0); in cptpf_device_init()
A Dotx2_cptvf_main.c405 cptvf->blkaddr = BLKADDR_CPT0; in otx2_cptvf_probe()
/drivers/net/ethernet/marvell/octeontx2/af/
A Drvu_cpt.c55 reg = rvu_read64(rvu, BLKADDR_CPT0, CPT_AF_CONSTANTS1); in cpt_max_engines_get()
253 cpt_unregister_interrupts(rvu, BLKADDR_CPT0); in rvu_cpt_unregister_interrupts()
380 ret = cpt_register_interrupts(rvu, BLKADDR_CPT0); in rvu_cpt_register_interrupts()
437 blkaddr = req_blkaddr ? req_blkaddr : BLKADDR_CPT0; in validate_and_get_cpt_blkaddr()
438 if (blkaddr != BLKADDR_CPT0 && blkaddr != BLKADDR_CPT1) in validate_and_get_cpt_blkaddr()
550 ret = cpt_lf_free(rvu, req, BLKADDR_CPT0); in rvu_mbox_handler_cpt_lf_free()
1198 cpt_idx = (blkaddr == BLKADDR_CPT0) ? 0 : 1; in cpt_inline_inb_lf_cmd_send()
1245 blkaddr = (nix_blkaddr == BLKADDR_NIX1) ? BLKADDR_CPT1 : BLKADDR_CPT0; in rvu_cpt_ctx_flush()
1301 if (is_block_implemented(rvu->hw, BLKADDR_CPT0) && !is_rvu_otx2(rvu) && in rvu_cpt_init()
1309 reg_val = rvu_read64(rvu, BLKADDR_CPT0, CPT_AF_RXC_CFG1); in rvu_cpt_init()
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A Drvu.c285 blkaddr = BLKADDR_CPT0; in rvu_get_blkaddr()
324 blkaddr = BLKADDR_CPT0; in rvu_get_blkaddr()
389 case BLKADDR_CPT0: in rvu_update_rsrc_map()
539 rvu_block_reset(rvu, BLKADDR_CPT0, CPT_AF_BLK_RST); in rvu_reset_all_blocks()
884 blkid = (blkaddr == BLKADDR_CPT0) ? 0 : 1; in rvu_setup_cpt_hw_resource()
1059 err = rvu_setup_cpt_hw_resource(rvu, BLKADDR_CPT0); in rvu_setup_hw_resources()
1264 case BLKADDR_CPT0: in rvu_get_rsrc_mapcount()
1537 BLKADDR_CPT0; in rvu_get_attach_blkaddr()
1935 block = &hw->block[BLKADDR_CPT0]; in rvu_mbox_handler_free_rsrc_cnt()
2747 else if ((block->addr == BLKADDR_CPT0) || in rvu_blklf_teardown()
[all …]
A Drvu_struct.h28 BLKADDR_CPT0 = 0xaULL, enumerator
A Drvu_debugfs.c3922 if (blkaddr == BLKADDR_CPT0) { in rvu_dbg_cpt_init()
3925 ctx->blkaddr = BLKADDR_CPT0; in rvu_dbg_cpt_init()
3990 rvu_dbg_cpt_init(rvu, BLKADDR_CPT0); in rvu_dbg_init()
A Drvu_nix.c5520 cpt_blkaddr = (cpt_idx == 0) ? BLKADDR_CPT0 : in nix_inline_ipsec_cfg()
5553 if (!is_block_implemented(rvu->hw, BLKADDR_CPT0)) in rvu_mbox_handler_nix_inline_ipsec_cfg()
5570 if (!is_block_implemented(rvu->hw, BLKADDR_CPT0)) in rvu_mbox_handler_nix_read_inline_ipsec_cfg()
5594 if (!is_block_implemented(rvu->hw, BLKADDR_CPT0)) in rvu_mbox_handler_nix_inline_ipsec_lf_cfg()
/drivers/net/ethernet/marvell/octeontx2/nic/
A Dotx2_common.h669 blkaddr = BLKADDR_CPT0; in otx2_get_regaddr()

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