| /drivers/mmc/host/ |
| A D | mmci_qcom_dml.c | 24 #define BYPASS BIT(16) macro
149 config &= ~BYPASS; in qcom_dma_setup()
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| /drivers/infiniband/hw/hfi1/ |
| A D | trace.h | 13 packettype_name(BYPASS))
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| A D | chip.c | 646 /*11*/ FLAG_ENTRY0("BypassErr", SEEI(BYPASS)),
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| /drivers/crypto/ccree/ |
| A D | cc_sram_mgr.c | 87 set_flow_mode(&seq[idx], BYPASS); in cc_set_sram_desc()
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| A D | cc_aead.c | 494 set_flow_mode(&desc[idx], BYPASS); in cc_get_plain_hmac_key()
503 set_flow_mode(&desc[idx], BYPASS); in cc_get_plain_hmac_key()
512 set_flow_mode(&desc[idx], BYPASS); in cc_get_plain_hmac_key()
523 set_flow_mode(&desc[idx], BYPASS); in cc_get_plain_hmac_key()
1180 set_flow_mode(&desc[*seq_size], BYPASS); in cc_mlli_to_sram()
1800 cc_proc_cipher_desc(req, BYPASS, desc, seq_size); in cc_gcm()
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| A D | cc_hw_queue_defs.h | 94 BYPASS = 0, enumerator
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| A D | cc_hash.c | 812 set_flow_mode(&desc[idx], BYPASS); in cc_hash_setkey()
823 set_flow_mode(&desc[idx], BYPASS); in cc_hash_setkey()
832 set_flow_mode(&desc[idx], BYPASS); in cc_hash_setkey()
843 set_flow_mode(&desc[idx], BYPASS); in cc_hash_setkey()
2190 set_flow_mode(&desc[idx], BYPASS); in cc_set_desc()
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| A D | cc_request_mgr.c | 174 set_flow_mode(&req_mgr_h->compl_desc, BYPASS); in cc_req_mgr_init()
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| A D | cc_cipher.c | 786 set_flow_mode(&desc[*seq_size], BYPASS); in cc_setup_mlli_desc()
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| /drivers/gpu/drm/radeon/ |
| A D | rv740d.h | 59 #define BYPASS (1 << 19) macro
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| A D | rv740_dpm.c | 351 mpll_dq_func_cntl_2 |= BYPASS | BIAS_GEN_PDNB | RESET_EN; in rv740_populate_smc_acpi_state()
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| A D | rv770d.h | 132 #define BYPASS (1 << 19) macro
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| A D | nid.h | 574 #define BYPASS (1 << 19) macro
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| A D | evergreend.h | 112 #define BYPASS (1 << 19) macro
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| A D | cypress_dpm.c | 1400 mpll_dq_func_cntl_2 |= BIAS_GEN_PDNB | RESET_EN | BYPASS; in cypress_populate_smc_acpi_state()
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| A D | ni_dpm.c | 1870 mpll_dq_func_cntl_2 |= BIAS_GEN_PDNB | RESET_EN | BYPASS; in ni_populate_smc_acpi_state()
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| /drivers/net/ethernet/marvell/octeontx2/af/ |
| A D | common.h | 236 BYPASS = 0x1, enumerator
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| A D | rvu_debugfs.c | 1472 ndc_cache_stats(s, blk_addr, BYPASS, NDC_READ_TRANS); in ndc_blk_cache_stats()
1474 ndc_cache_stats(s, blk_addr, BYPASS, NDC_WRITE_TRANS); in ndc_blk_cache_stats()
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| /drivers/pci/controller/dwc/ |
| A D | pcie-qcom.c | 129 #define BYPASS BIT(4) macro
726 val |= BYPASS; in qcom_pcie_post_init_2_3_2()
1008 val |= BYPASS; in qcom_pcie_init_2_7_0()
1216 writel(BYPASS | MSTR_AXI_CLK_EN | AHB_CLK_EN, in qcom_pcie_post_init_2_9_0()
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| /drivers/gpu/drm/nouveau/dispnv50/ |
| A D | wndwc37e.c | 182 NVDEF(NVC37E, SET_PARAMS, INPUT_RANGE, BYPASS) | in wndwc37e_image_set()
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| /drivers/net/ethernet/huawei/hinic/ |
| A D | hinic_hw_api_cmd.c | 67 BYPASS = 1, enumerator
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| /drivers/iommu/ |
| A D | msm_iommu_hw-8xxx.h | 219 #define SET_BYPASS(b, v) SET_GLOBAL_FIELD(b, ESR, BYPASS, v)
336 #define GET_BYPASS(b) GET_GLOBAL_FIELD(b, ESR, BYPASS)
878 #define BYPASS (BYPASS_MASK << BYPASS_SHIFT) macro
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| /drivers/gpu/drm/amd/include/ |
| A D | soc24_enum.h | 1240 BYPASS = 0x00000000, enumerator
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| A D | soc21_enum.h | 1089 BYPASS = 0x00000000, enumerator
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