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Searched refs:CFG_REG (Results 1 – 2 of 2) sorted by relevance

/drivers/clk/qcom/
A Dclk-rcg2.c35 #define CFG_REG 0x4 macro
49 #define RCG_CFG_OFFSET(rcg) ((rcg)->cmd_rcgr + (rcg)->cfg_off + CFG_REG)
913 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, in clk_edp_pixel_set_rate()
963 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, in clk_edp_pixel_determine_rate()
1084 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg); in clk_byte2_set_rate()
1160 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg); in clk_pixel_set_rate()
1177 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, in clk_pixel_set_rate()
1292 ret = regmap_write(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, cfg); in clk_gfx3d_set_rate_and_parent()
1455 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &rcg->parked_cfg); in clk_rcg2_shared_disable()
1467 regmap_write(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, in clk_rcg2_shared_disable()
[all …]
/drivers/pci/controller/
A Dpci-aardvark.c167 #define CFG_REG (LMI_BASE_ADDR + 0x0) macro
307 val = advk_readl(pcie, CFG_REG); in advk_pcie_ltssm_state()

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