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Searched refs:CG_UPLL_FUNC_CNTL (Results 1 – 10 of 10) sorted by relevance

/drivers/gpu/drm/radeon/
A Drv770.c70 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK); in rv770_set_uvd_clocks()
88 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~(UPLL_RESET_MASK | UPLL_SLEEP_MASK)); in rv770_set_uvd_clocks()
91 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK); in rv770_set_uvd_clocks()
94 r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL); in rv770_set_uvd_clocks()
99 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK); in rv770_set_uvd_clocks()
102 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_REF_DIV(1), ~UPLL_REF_DIV_MASK); in rv770_set_uvd_clocks()
117 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK); in rv770_set_uvd_clocks()
122 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK); in rv770_set_uvd_clocks()
125 r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL); in rv770_set_uvd_clocks()
A Devergreen.c1205 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK); in evergreen_set_uvd_clocks()
1216 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_VCO_MODE_MASK, ~UPLL_VCO_MODE_MASK); in evergreen_set_uvd_clocks()
1219 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK); in evergreen_set_uvd_clocks()
1220 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_SLEEP_MASK); in evergreen_set_uvd_clocks()
1223 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK); in evergreen_set_uvd_clocks()
1227 r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL); in evergreen_set_uvd_clocks()
1232 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK); in evergreen_set_uvd_clocks()
1241 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_REF_DIV_MASK); in evergreen_set_uvd_clocks()
1257 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK); in evergreen_set_uvd_clocks()
1262 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK); in evergreen_set_uvd_clocks()
[all …]
A Dr600.c214 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~( in r600_set_uvd_clocks()
223 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK); in r600_set_uvd_clocks()
243 r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL); in r600_set_uvd_clocks()
248 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK); in r600_set_uvd_clocks()
252 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_REFCLK_SRC_SEL_MASK, in r600_set_uvd_clocks()
256 WREG32_P(CG_UPLL_FUNC_CNTL, in r600_set_uvd_clocks()
272 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK); in r600_set_uvd_clocks()
277 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK); in r600_set_uvd_clocks()
282 r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL); in r600_set_uvd_clocks()
A Dsi.c6986 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK); in si_set_uvd_clocks()
7003 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_VCO_MODE_MASK, ~UPLL_VCO_MODE_MASK); in si_set_uvd_clocks()
7006 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_SLEEP_MASK); in si_set_uvd_clocks()
7009 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK); in si_set_uvd_clocks()
7013 r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL); in si_set_uvd_clocks()
7018 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK); in si_set_uvd_clocks()
7027 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_REF_DIV_MASK); in si_set_uvd_clocks()
7043 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK); in si_set_uvd_clocks()
7048 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK); in si_set_uvd_clocks()
7050 r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL); in si_set_uvd_clocks()
A Drv770d.h42 #define CG_UPLL_FUNC_CNTL 0x718 macro
A Dsid.h127 #define CG_UPLL_FUNC_CNTL 0x634 macro
A Devergreend.h348 #define CG_UPLL_FUNC_CNTL 0x718 macro
A Dr600d.h1556 #define CG_UPLL_FUNC_CNTL 0x7e0 macro
/drivers/gpu/drm/amd/amdgpu/
A Dsi.c1801 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK); in si_set_uvd_clocks()
1818 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_VCO_MODE_MASK, ~UPLL_VCO_MODE_MASK); in si_set_uvd_clocks()
1821 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_SLEEP_MASK); in si_set_uvd_clocks()
1824 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK); in si_set_uvd_clocks()
1828 r = si_uvd_send_upll_ctlreq(adev, CG_UPLL_FUNC_CNTL); in si_set_uvd_clocks()
1833 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK); in si_set_uvd_clocks()
1842 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_REF_DIV_MASK); in si_set_uvd_clocks()
1860 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK); in si_set_uvd_clocks()
1865 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK); in si_set_uvd_clocks()
1867 r = si_uvd_send_upll_ctlreq(adev, CG_UPLL_FUNC_CNTL); in si_set_uvd_clocks()
A Dsid.h49 #define CG_UPLL_FUNC_CNTL 0x18d macro

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