Searched refs:CLAMP_IO (Results 1 – 25 of 27) sorted by relevance
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| /drivers/clk/qcom/ |
| A D | gdsc.h | 62 #define CLAMP_IO BIT(1) macro
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| A D | gpucc-sdm845.c | 139 .flags = CLAMP_IO | AON_RESET | POLL_CFG_GDSCR,
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| A D | gpucc-sc7180.c | 178 .flags = CLAMP_IO,
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| A D | gdsc.c | 273 if (sc->flags & CLAMP_IO) { in gdsc_enable()
360 if (sc->flags & CLAMP_IO) in gdsc_disable()
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| A D | gpucc-sm8150.c | 241 .flags = CLAMP_IO | AON_RESET | POLL_CFG_GDSCR,
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| A D | gpucc-sm8250.c | 249 .flags = CLAMP_IO | AON_RESET | POLL_CFG_GDSCR,
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| A D | gpucc-sdm660.c | 254 .flags = CLAMP_IO | SW_RESET | AON_RESET | NO_RET_PERIPH,
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| A D | gpucc-msm8998.c | 270 .flags = CLAMP_IO | SW_RESET | AON_RESET | NO_RET_PERIPH,
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| A D | gpucc-qcm2290.c | 317 .flags = CLAMP_IO | AON_RESET | SW_RESET,
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| A D | gpucc-sc8280xp.c | 402 .flags = CLAMP_IO | RETAIN_FF_ENABLE,
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| A D | gpucc-sm6375.c | 380 .flags = CLAMP_IO | SW_RESET | AON_RESET,
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| A D | gpucc-sar2130p.c | 417 .flags = CLAMP_IO | AON_RESET | SW_RESET,
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| A D | gpucc-sc7280.c | 406 .flags = CLAMP_IO | RETAIN_FF_ENABLE,
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| A D | gpucc-sm6115.c | 417 .flags = CLAMP_IO | SW_RESET | VOTABLE,
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| A D | gpucc-sm6350.c | 437 .flags = CLAMP_IO | POLL_CFG_GDSCR,
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| A D | gpucc-x1p42100.c | 474 .flags = CLAMP_IO | POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
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| A D | gpucc-sm8350.c | 528 .flags = CLAMP_IO | AON_RESET | POLL_CFG_GDSCR,
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| A D | gpucc-sm8550.c | 500 .flags = CLAMP_IO | POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
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| A D | gpucc-sm8650.c | 565 .flags = CLAMP_IO | AON_RESET | SW_RESET | POLL_CFG_GDSCR,
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| A D | gpucc-x1e80100.c | 557 .flags = CLAMP_IO | AON_RESET | SW_RESET | POLL_CFG_GDSCR,
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| A D | gpucc-sm4450.c | 694 .flags = CLAMP_IO | AON_RESET | SW_RESET | POLL_CFG_GDSCR,
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| A D | gpucc-sm8450.c | 692 .flags = CLAMP_IO | AON_RESET | SW_RESET | POLL_CFG_GDSCR,
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| A D | mmcc-msm8994.c | 2380 .flags = CLAMP_IO,
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| A D | gcc-msm8917.c | 3027 .flags = CLAMP_IO,
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| A D | mmcc-msm8996.c | 3328 .flags = CLAMP_IO,
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Completed in 46 milliseconds
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