Searched refs:CLK_CFG_0_CLR (Results 1 – 2 of 2) sorted by relevance
| /drivers/clk/mediatek/ |
| A D | clk-mt6735-topckgen.c | 16 #define CLK_CFG_0_CLR 0x48 macro
335 …(CLK_TOP_AXI_SEL, "axi_sel", axi_sel_parents, CLK_CFG_0, CLK_CFG_0_SET, CLK_CFG_0_CLR, 0, 3, 0, 0),
336 …(CLK_TOP_MEM_SEL, "mem_sel", mem_sel_parents, CLK_CFG_0, CLK_CFG_0_SET, CLK_CFG_0_CLR, 8, 1, 0, 0),
337 …PHY_SEL, "ddrphycfg_sel", ddrphycfg_parents, CLK_CFG_0, CLK_CFG_0_SET, CLK_CFG_0_CLR, 16, 1, 0, 0),
338 …D(CLK_TOP_MM_SEL, "mm_sel", mm_sel_parents, CLK_CFG_0, CLK_CFG_0_SET, CLK_CFG_0_CLR, 24, 3, 31, 0,…
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| A D | clk-mt6765.c | 43 #define CLK_CFG_0_CLR 0x48 macro
369 CLK_CFG_0, CLK_CFG_0_SET, CLK_CFG_0_CLR,
373 CLK_CFG_0, CLK_CFG_0_SET, CLK_CFG_0_CLR,
377 CLK_CFG_0_SET, CLK_CFG_0_CLR, 16, 3, 23,
380 CLK_CFG_0_SET, CLK_CFG_0_CLR, 24, 3, 31,
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Completed in 6 milliseconds