| /drivers/clk/ |
| A D | clk-loongson2.c | 61 #define CLK_DIV(_id, _name, _pname, _offset, _dshift, _dwidth) \ macro
123 CLK_DIV(LOONGSON2_NODE_CLK, "clk_node", "pll_node", 0, 24, 6),
124 CLK_DIV(LOONGSON2_DDR_CLK, "clk_ddr", "pll_ddr", 0x8, 24, 6),
125 CLK_DIV(LOONGSON2_HDA_CLK, "clk_hda", "pll_ddr", 0xc, 8, 6),
126 CLK_DIV(LOONGSON2_GPU_CLK, "clk_gpu", "pll_soc", 0x10, 24, 6),
127 CLK_DIV(LOONGSON2_DC_CLK, "clk_sb", "pll_soc", 0x14, 0, 6),
128 CLK_DIV(LOONGSON2_GMAC_CLK, "clk_gmac", "pll_soc", 0x14, 8, 6),
129 CLK_DIV(LOONGSON2_PIX0_CLK, "clk_pix0", "pll_pix0", 0x18, 24, 6),
130 CLK_DIV(LOONGSON2_PIX1_CLK, "clk_pix1", "pll_pix1", 0x20, 24, 6),
144 CLK_DIV(LOONGSON2_NODE_CLK, "clk_node", "pll_node", 0x8, 0, 6),
[all …]
|
| A D | clk-bm1880.c | 183 #define CLK_DIV(_id, _name, _parent, _reg, _shift, _width, _initval, \ macro
372 CLK_DIV(BM1880_CLK_DIV_0_RV, "clk_div_0_rv", &bm1880_pll_clks[1].hw,
374 CLK_DIV(BM1880_CLK_DIV_1_RV, "clk_div_1_rv", &bm1880_pll_clks[2].hw,
376 CLK_DIV(BM1880_CLK_DIV_UART_500M, "clk_div_uart_500m", &bm1880_pll_clks[2].hw,
378 CLK_DIV(BM1880_CLK_DIV_0_AXI1, "clk_div_0_axi1", &bm1880_pll_clks[0].hw,
381 CLK_DIV(BM1880_CLK_DIV_1_AXI1, "clk_div_1_axi1", &bm1880_pll_clks[2].hw,
384 CLK_DIV(BM1880_CLK_DIV_0_AXI6, "clk_div_0_axi6", &bm1880_pll_clks[2].hw,
387 CLK_DIV(BM1880_CLK_DIV_1_AXI6, "clk_div_1_axi6", &bm1880_pll_clks[0].hw,
390 CLK_DIV(BM1880_CLK_DIV_12M_USB, "clk_div_12m_usb", &bm1880_pll_clks[2].hw,
|
| /drivers/misc/cardreader/ |
| A D | rtsx_usb.c | 451 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, CLK_DIV, CLK_CHANGE, CLK_CHANGE); in rtsx_usb_switch_clock()
452 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, CLK_DIV, in rtsx_usb_switch_clock()
478 ret = rtsx_usb_write_register(ucr, CLK_DIV, CLK_CHANGE, 0); in rtsx_usb_switch_clock()
581 ret = rtsx_usb_write_register(ucr, CLK_DIV, CLK_CHANGE, 0x00); in rtsx_usb_init_chip()
|
| A D | rts5228.c | 650 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV, in rts5228_pci_switch_clock()
|
| A D | rts5261.c | 729 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV, in rts5261_pci_switch_clock()
|
| A D | rtsx_pcr.c | 771 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV, in rtsx_pci_switch_clock()
1220 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV, 0x07, 0x07); in rtsx_pci_init_hw()
|
| A D | rts5264.c | 873 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV, in rts5264_pci_switch_clock()
|
| /drivers/clk/nxp/ |
| A D | clk-lpc32xx.c | 1047 CLK_DIV, enumerator
1132 .type = CLK_DIV, \
1401 case CLK_DIV: in lpc32xx_clk_register()
1421 else if (clk_hw->type == CLK_DIV) in lpc32xx_clk_register()
|
| /drivers/mmc/host/ |
| A D | rtsx_usb_sdmmc.c | 585 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, CLK_DIV, CLK_CHANGE, CLK_CHANGE); in sd_change_phase()
597 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, CLK_DIV, CLK_CHANGE, 0); in sd_change_phase()
|
| /drivers/gpu/drm/bridge/cadence/ |
| A D | cdns-dsi-core.c | 98 #define CLK_DIV(x) (x) macro
907 writel(CLK_DIV(div) | HSTX_TIMEOUT(tmp), in cdns_dsi_bridge_atomic_pre_enable()
|