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Searched refs:CONTROL (Results 1 – 25 of 63) sorted by relevance

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/drivers/parport/
A Dparport_gsc.c83 s->u.pc.ctr = parport_readb (CONTROL (p)); in parport_gsc_save_state()
88 parport_writeb (s->u.pc.ctr, CONTROL (p)); in parport_gsc_restore_state()
147 parport_writeb (w, CONTROL (pb)); in parport_SPP_supported()
154 r = parport_readb (CONTROL (pb)); in parport_SPP_supported()
157 parport_writeb (w, CONTROL (pb)); in parport_SPP_supported()
158 r = parport_readb (CONTROL (pb)); in parport_SPP_supported()
159 parport_writeb (0xc, CONTROL (pb)); in parport_SPP_supported()
A Dparport_gsc.h47 #define CONTROL(p) ((p)->base + 0x2) macro
101 parport_writeb (ctr, CONTROL (p)); in __parport_gsc_frob_control()
A Dparport_pc.c259 outb(c, CONTROL(p)); in parport_pc_restore_state()
1430 outb(w, CONTROL(pb)); in parport_SPP_supported()
1437 r = inb(CONTROL(pb)); in parport_SPP_supported()
1440 outb(w, CONTROL(pb)); in parport_SPP_supported()
1441 r = inb(CONTROL(pb)); in parport_SPP_supported()
1442 outb(0xc, CONTROL(pb)); in parport_SPP_supported()
1502 outb(r, CONTROL(pb)); in parport_ECR_present()
1506 r = inb(CONTROL(pb)); in parport_ECR_present()
1521 outb(0xc, CONTROL(pb)); in parport_ECR_present()
1529 outb(0xc, CONTROL(pb)); in parport_ECR_present()
[all …]
/drivers/gpu/drm/imx/dc/
A Ddc-fw.c30 #define CONTROL 0x170 macro
62 regmap_reg_range(CONTROL, CONTROL),
78 .max_register = CONTROL,
88 regmap_write_bits(fu->reg_cfg, CONTROL, INPUTSELECT_MASK, in dc_fw_set_fmt()
90 regmap_write_bits(fu->reg_cfg, CONTROL, RASTERMODE_MASK, in dc_fw_set_fmt()
A Ddc-ed.c35 #define CONTROL 0xc macro
89 regmap_reg_range(CONTROL, CONTROL),
105 .max_register = CONTROL,
175 regmap_write_bits(ed->reg_cfg, CONTROL, GAMMAAPPLYENABLE, 0); in dc_ed_disable_gamma_apply()
A Ddc-lb.c33 #define CONTROL 0xc macro
210 regmap_write_bits(lb->reg_cfg, CONTROL, CTRL_MODE_MASK, mode); in dc_lb_mode()
/drivers/clocksource/
A Dtimer-digicolor.c48 #define CONTROL(t) ((t)*8) macro
72 writeb(CONTROL_DISABLE, dt->base + CONTROL(dt->timer_id)); in dc_timer_disable()
78 writeb(CONTROL_ENABLE | mode, dt->base + CONTROL(dt->timer_id)); in dc_timer_enable()
180 writeb(CONTROL_DISABLE, dc_timer_dev.base + CONTROL(TIMER_B)); in digicolor_timer_init()
182 writeb(CONTROL_ENABLE, dc_timer_dev.base + CONTROL(TIMER_B)); in digicolor_timer_init()
/drivers/hwmon/
A Dadt7475.c31 CONTROL = 3, enumerator
801 data->pwm[CONTROL][sattr->index] = in pwm_store()
919 data->pwm[CONTROL][index] &= ~0xE0; in hw_set_pwm()
923 data->pwm[CONTROL][index]); in hw_set_pwm()
1770 data->pwm[CONTROL][cfg.index] = ret; in adt7475_fan_pwm_config()
1777 data->pwm[CONTROL][cfg.index] &= ~0xE0; in adt7475_fan_pwm_config()
1781 data->pwm[CONTROL][cfg.index]); in adt7475_fan_pwm_config()
2026 v = (data->pwm[CONTROL][index] >> 5) & 7; in adt7475_read_pwm()
2039 data->pwm[CONTROL][index] &= ~0xE0; in adt7475_read_pwm()
2040 data->pwm[CONTROL][index] |= (7 << 5); in adt7475_read_pwm()
[all …]
/drivers/bluetooth/
A Dbt3c_cs.c113 #define CONTROL 4 macro
349 iir = inb(iobase + CONTROL); in bt3c_interrupt()
370 outb(iir, iobase + CONTROL); in bt3c_interrupt()
524 outb(inb(iobase + CONTROL) | 0x40, iobase + CONTROL); in bt3c_load_firmware()
/drivers/watchdog/
A Dmachzwd.c52 #define CONTROL 0x10 /* 16 */ macro
155 return zf_readw(CONTROL); in zf_get_control()
160 zf_writew(CONTROL, new); in zf_set_control()
/drivers/gpu/drm/amd/display/dc/optc/dcn31/
A Ddcn31_optc.c104 REG_UPDATE(CONTROL, in optc31_enable_crtc()
141 REG_UPDATE(CONTROL, in optc31_disable_crtc()
163 REG_UPDATE(CONTROL, in optc31_immediate_disable_crtc()
/drivers/gpu/drm/amd/display/dc/optc/dcn314/
A Ddcn314_optc.c114 REG_UPDATE(CONTROL, in optc314_enable_crtc()
141 REG_UPDATE(CONTROL, in optc314_disable_crtc()
/drivers/gpu/drm/amd/display/dc/dce/
A Ddce_opp.h78 SRI(CONTROL, FMT_MEMORY, id)
82 SRI(CONTROL, FMT_MEMORY, id)
296 uint32_t CONTROL; member
A Ddce_opp.c586 REG_GET(CONTROL, in program_formatter_420_memory()
593 REG_UPDATE(CONTROL, in program_formatter_420_memory()
/drivers/gpu/drm/amd/display/dc/optc/dcn32/
A Ddcn32_optc.c154 REG_UPDATE(CONTROL, in optc32_enable_crtc()
191 REG_UPDATE(CONTROL, in optc32_disable_crtc()
/drivers/media/usb/uvc/
A Duvc_ctrl.c1195 uvc_dbg(chain->dev, CONTROL, "Control 0x%08x not found\n", in uvc_find_control()
2687 uvc_dbg(dev, CONTROL, in uvc_ctrl_fill_xu_info()
2700 uvc_dbg(dev, CONTROL, in uvc_ctrl_fill_xu_info()
2708 uvc_dbg(dev, CONTROL, in uvc_ctrl_fill_xu_info()
2738 uvc_dbg(dev, CONTROL, in uvc_ctrl_init_xu_ctrl()
2769 uvc_dbg(chain->dev, CONTROL, "Extension unit %u not found\n", in uvc_xu_ctrl_query()
2785 uvc_dbg(chain->dev, CONTROL, "Control %pUl/%u not found\n", in uvc_xu_ctrl_query()
3038 uvc_dbg(dev, CONTROL, in uvc_ctrl_add_mapping()
3085 uvc_dbg(dev, CONTROL, in uvc_ctrl_add_mapping()
3096 uvc_dbg(dev, CONTROL, in uvc_ctrl_add_mapping()
[all …]
/drivers/net/ethernet/smsc/
A Dsmc9194.c338 outw( inw( ioaddr + CONTROL ) | CTL_AUTO_RELEASE , ioaddr + CONTROL ); in smc_reset()
398 outw( inw( ioaddr + CONTROL ), CTL_POWERDOWN, ioaddr + CONTROL ); in smc_shutdown()
A Dsmc91c92_cs.c191 #define CONTROL 12 macro
553 outw((CTL_RELOAD | CTL_EE_SELECT), ioaddr + CONTROL); in mot_setup()
557 wait = ((CTL_RELOAD | CTL_STORE) & inw(ioaddr + CONTROL)); in mot_setup()
775 outw(0, ioaddr + CONTROL); in check_sig()
1105 outw(CTL_POWERDOWN, ioaddr + CONTROL ); in smc_close()
1336 outw(CTL_AUTO_RELEASE | 0x0000, ioaddr + CONTROL); in smc_eph_irq()
1338 ioaddr + CONTROL); in smc_eph_irq()
1664 ioaddr + CONTROL); in smc_reset()
A Dsmc9194.h104 #define CONTROL 12 macro
/drivers/gpu/drm/amd/display/dc/optc/dcn10/
A Ddcn10_optc.c278 REG_UPDATE(CONTROL, in optc1_program_timing()
383 REG_UPDATE_2(CONTROL, in optc1_set_vtg_params()
387 REG_UPDATE(CONTROL, VTG0_VCOUNT_INIT, v_init); in optc1_set_vtg_params()
538 REG_UPDATE(CONTROL, in optc1_enable_crtc()
566 REG_UPDATE(CONTROL, in optc1_disable_crtc()
/drivers/scsi/
A Daha1542.h29 #define CONTROL(base) STATUS(base) macro
A Daha1542.c78 outb(IRST, CONTROL(base)); in aha1542_intr_reset()
220 outb(SRST | IRST /*|SCRST */ , CONTROL(sh->io_port)); in aha1542_test_port()
254 outb(IRST, CONTROL(sh->io_port)); in aha1542_test_port()
937 outb(reset_cmd, CONTROL(cmd->device->host->io_port)); in aha1542_reset()
/drivers/gpu/drm/amd/display/dc/optc/dcn35/
A Ddcn35_optc.c121 REG_UPDATE(CONTROL, in optc35_enable_crtc()
158 REG_UPDATE(CONTROL, in optc35_disable_crtc()
/drivers/gpu/drm/amd/display/dc/optc/dcn401/
A Ddcn401_optc.c189 REG_UPDATE(CONTROL, in optc401_enable_crtc()
226 REG_UPDATE(CONTROL, in optc401_disable_crtc()
/drivers/i3c/master/mipi-i3c-hci/
A Ddma.c187 rhs_reg_write(CONTROL, 0); in hci_dma_cleanup()
202 regval = rhs_reg_read(CONTROL); in hci_dma_init()
218 rhs_reg_write(CONTROL, regval); in hci_dma_init()

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