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Searched refs:CRTC5_REGISTER_OFFSET (Results 1 – 7 of 7) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
A Dvid.h38 #define CRTC5_REGISTER_OFFSET (0x459c - 0x1b9c) macro
A Dcikd.h44 #define CRTC5_REGISTER_OFFSET (0x4a7c - 0x1b7c) macro
A Dsid.h640 #define CRTC5_REGISTER_OFFSET (0x4a7c - 0x1b7c) //(0x129f0 - 0x6df0)/4 macro
A Ddce_v8_0.c63 CRTC5_REGISTER_OFFSET
81 CRTC5_REGISTER_OFFSET,
2950 reg_block = CRTC5_REGISTER_OFFSET; in dce_v8_0_set_crtc_vblank_interrupt_state()
3001 reg_block = CRTC5_REGISTER_OFFSET; in dce_v8_0_set_crtc_vline_interrupt_state()
A Ddce_v6_0.c74 CRTC5_REGISTER_OFFSET
93 CRTC5_REGISTER_OFFSET,
2978 reg_block = CRTC5_REGISTER_OFFSET; in dce_v6_0_set_crtc_vblank_interrupt_state()
A Ddce_v10_0.c63 CRTC5_REGISTER_OFFSET,
2754 amdgpu_crtc->crtc_offset = CRTC5_REGISTER_OFFSET; in dce_v10_0_crtc_init()
A Ddce_v11_0.c64 CRTC5_REGISTER_OFFSET,
2867 amdgpu_crtc->crtc_offset = CRTC5_REGISTER_OFFSET; in dce_v11_0_crtc_init()

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