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Searched refs:CTRL_STATUS (Results 1 – 3 of 3) sorted by relevance

/drivers/media/platform/qcom/iris/
A Diris_vpu_common.c23 #define CTRL_STATUS (CPU_CS_BASE_OFFS + 0x4C) macro
120 ctrl_status = readl(core->reg_base + CTRL_STATUS); in iris_vpu_boot_firmware()
177 ctrl_status = readl(core->reg_base + CTRL_STATUS); in iris_vpu_prepare_pc()
192 ret = readl_poll_timeout(core->reg_base + CTRL_STATUS, val, in iris_vpu_prepare_pc()
205 ctrl_status = readl(core->reg_base + CTRL_STATUS); in iris_vpu_prepare_pc()
/drivers/mtd/nand/raw/
A Dcadence-nand-controller.c86 #define CTRL_STATUS 0x0118 macro
584 if (cadence_nand_wait_for_value(cdns_ctrl, CTRL_STATUS, in cadence_nand_set_ecc_enable()
637 if (cadence_nand_wait_for_value(cdns_ctrl, CTRL_STATUS, in cadence_nand_set_skip_marker_val()
659 if (cadence_nand_wait_for_value(cdns_ctrl, CTRL_STATUS, in cadence_nand_set_skip_bytes_conf()
705 if (cadence_nand_wait_for_value(cdns_ctrl, CTRL_STATUS, in cadence_nand_set_access_width16()
839 if (cadence_nand_wait_for_value(cdns_ctrl, CTRL_STATUS, in cadence_nand_generic_cmd_send()
1162 status = cadence_nand_wait_for_value(cdns_ctrl, CTRL_STATUS, in cadence_nand_hw_init()
1353 if (cadence_nand_wait_for_value(cdns_ctrl, CTRL_STATUS, in cadence_nand_select_target()
2697 if (cadence_nand_wait_for_value(cdns_ctrl, CTRL_STATUS, in cadence_nand_attach_chip()
/drivers/platform/x86/intel/
A Dsdsi.c71 #define CTRL_STATUS GENMASK(15, 8) macro
185 status = FIELD_GET(CTRL_STATUS, control); in sdsi_mbox_poll()

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