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Searched refs:CWB_0 (Results 1 – 8 of 8) sorted by relevance

/drivers/gpu/drm/msm/disp/dpu1/
A Ddpu_rm.h35 struct dpu_hw_blk *cwb_blks[CWB_MAX - CWB_0];
A Ddpu_kms.h135 uint32_t cwb_to_crtc_id[CWB_MAX - CWB_0];
A Ddpu_hw_mdss.h262 CWB_0 = 0x1, enumerator
A Ddpu_hw_ctl.c333 ctx->pending_cwb_flush_mask |= BIT(cwb - CWB_0); in dpu_hw_ctl_update_pending_flush_cwb_v1()
A Ddpu_rm.c138 rm->cwb_blks[cwb->id - CWB_0] = &hw->base; in dpu_rm_init()
A Ddpu_encoder.c1208 cwb_mask |= BIT(dpu_enc->hw_cwb[i]->idx - CWB_0); in dpu_encoder_virt_atomic_mode_set()
/drivers/gpu/drm/msm/disp/dpu1/catalog/
A Ddpu_10_0_sm8650.h333 .name = "cwb_0", .id = CWB_0,
A Ddpu_12_0_sm8750.h375 .name = "cwb_0", .id = CWB_0,

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