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Searched refs:D2VGA_CONTROL (Results 1 – 10 of 10) sorted by relevance

/drivers/gpu/drm/radeon/
A Davivod.h51 #define D2VGA_CONTROL 0x0338 macro
/drivers/gpu/drm/amd/display/dc/hwss/dce/
A Ddce_hwseq.h250 SR(D2VGA_CONTROL), \
314 SR(D2VGA_CONTROL), \
364 SR(D2VGA_CONTROL), \
472 SR(D2VGA_CONTROL), \
532 SR(D2VGA_CONTROL), \
562 SR(D2VGA_CONTROL), \
660 uint32_t D2VGA_CONTROL; member
833 HWS_SF(, D2VGA_CONTROL, D2VGA_MODE_ENABLE, mask_sh),\
/drivers/gpu/drm/amd/display/dc/resource/dcn316/
A Ddcn316_resource.c719 SR(D2VGA_CONTROL), \
/drivers/gpu/drm/amd/display/dc/resource/dcn314/
A Ddcn314_resource.c734 SR(D2VGA_CONTROL), \
/drivers/gpu/drm/amd/display/dc/resource/dcn31/
A Ddcn31_resource.c725 SR(D2VGA_CONTROL), \
/drivers/gpu/drm/amd/display/dc/resource/dcn321/
A Ddcn321_resource.c574 SR(D2VGA_CONTROL), \
/drivers/gpu/drm/amd/display/dc/resource/dcn315/
A Ddcn315_resource.c724 SR(D2VGA_CONTROL), \
/drivers/gpu/drm/amd/display/dc/hwss/dcn10/
A Ddcn10_hwseq.c826 REG_GET(D2VGA_CONTROL, D2VGA_MODE_ENABLE, &in_vga2_mode); in dcn10_disable_vga()
835 REG_WRITE(D2VGA_CONTROL, 0); in dcn10_disable_vga()
/drivers/gpu/drm/amd/display/dc/resource/dcn32/
A Ddcn32_resource.c578 SR(D2VGA_CONTROL), \
/drivers/gpu/drm/amd/display/dc/hwss/dcn20/
A Ddcn20_hwseq.c385 REG_WRITE(D2VGA_CONTROL, 0); in dcn20_disable_vga()

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