Searched refs:DCC (Results 1 – 8 of 8) sorted by relevance
| /drivers/tty/hvc/ |
| A D | Kconfig | 81 bool "ARM JTAG DCC console"
86 This console uses the JTAG DCC on ARM to create a console under the HVC
91 bool "Use DCC only on CPU core 0"
95 Some external debuggers, do not handle reads/writes from/to DCC on more
96 than one CPU core. Each core has its own DCC device registers, so when a
97 CPU core reads or writes from/to DCC, it only accesses its own DCC device.
99 write to the console, it might write to a different DCC.
102 shows the DCC output only from that core's DCC. The result is that
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| /drivers/gpu/drm/amd/display/amdgpu_dm/ |
| A D | amdgpu_dm_plane.c | 412 AMD_FMT_MOD_SET(DCC, 1) | in amdgpu_dm_plane_add_gfx10_1_modifiers()
421 AMD_FMT_MOD_SET(DCC, 1) | in amdgpu_dm_plane_add_gfx10_1_modifiers()
477 AMD_FMT_MOD_SET(DCC, 1) | in amdgpu_dm_plane_add_gfx9_modifiers()
488 AMD_FMT_MOD_SET(DCC, 1) | in amdgpu_dm_plane_add_gfx9_modifiers()
499 AMD_FMT_MOD_SET(DCC, 1) | in amdgpu_dm_plane_add_gfx9_modifiers()
513 AMD_FMT_MOD_SET(DCC, 1) | in amdgpu_dm_plane_add_gfx9_modifiers()
568 AMD_FMT_MOD_SET(DCC, 1) | in amdgpu_dm_plane_add_gfx10_3_modifiers()
579 AMD_FMT_MOD_SET(DCC, 1) | in amdgpu_dm_plane_add_gfx10_3_modifiers()
589 AMD_FMT_MOD_SET(DCC, 1) | in amdgpu_dm_plane_add_gfx10_3_modifiers()
601 AMD_FMT_MOD_SET(DCC, 1) | in amdgpu_dm_plane_add_gfx10_3_modifiers()
[all …]
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| /drivers/gpu/drm/i915/ |
| A D | intel_mchbar_regs.h | 36 #define DCC _MMIO(MCHBAR_MIRROR_BASE + 0x200) macro
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| A D | i915_debugfs.c | 342 intel_uncore_read(uncore, DCC)); in i915_swizzle_info()
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| /drivers/gpu/drm/amd/amdgpu/ |
| A D | amdgpu_display.c | 668 if (AMD_FMT_MOD_GET(DCC, modifier)) in amdgpu_lookup_format_info()
742 AMD_FMT_MOD_SET(DCC, afb->gfx12_dcc) | in convert_tiling_flags_to_modifier_gfx12()
883 modifier |= AMD_FMT_MOD_SET(DCC, 1) | in convert_tiling_flags_to_modifier()
1134 AMD_FMT_MOD_GET(DCC, modifier)) { in amdgpu_display_verify_sizes()
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| /drivers/atm/ |
| A D | he.h | 657 #define DCC 0x807cc macro
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| A D | he.c | 1407 he_writel(he_dev, 0x0, DCC); in he_start()
2727 dcc += he_readl(he_dev, DCC); in he_proc_read()
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| /drivers/gpu/drm/i915/gt/ |
| A D | intel_ggtt_fencing.c | 669 u32 dcc = intel_uncore_read(uncore, DCC); in detect_bit_6_swizzle()
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