| /drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| A D | display_mode_vba_util_32.h | 338 bool DCCEnable[],
436 bool DCCEnable,
511 bool DCCEnable,
791 bool DCCEnable,
901 bool DCCEnable[],
952 bool DCCEnable[],
1039 bool DCCEnable[],
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| A D | display_mode_vba_util_32.c | 1774 bool DCCEnable[], in dml32_CalculateSurfaceSizeInMall() argument
2022 myPipe[k].DCCEnable, in dml32_CalculateVMRowAndSwath()
2096 myPipe[k].DCCEnable, in dml32_CalculateVMRowAndSwath()
2225 myPipe[k].DCCEnable, in dml32_CalculateVMRowAndSwath()
2264 bool DCCEnable, in dml32_CalculateVMAndRowBytes() argument
2372 if (DCCEnable != true) { in dml32_CalculateVMAndRowBytes()
2671 bool DCCEnable, in dml32_CalculateRowBandwidth() argument
4135 bool DCCEnable, in dml32_CalculateFlipSchedule() argument
4882 bool DCCEnable[], in dml32_CalculateMetaAndPTETimes() argument
5153 bool DCCEnable[], in dml32_CalculateVMGroupAndRequestTimes() argument
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| A D | display_mode_vba_32.c | 390 mode_lib->vba.DCCEnable, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
574 if (mode_lib->vba.DCCEnable[k]) in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1056 mode_lib->vba.DCCEnable[k], in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1298 mode_lib->vba.DCCEnable, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1349 mode_lib->vba.DCCEnable, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1392 mode_lib->vba.DCCEnable[k], in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1556 mode_lib->vba.DCCEnable, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1620 mode_lib->vba.DCCEnable, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2654 mode_lib->vba.DCCEnable, in dml32_ModeSupportAndSystemConfigurationFull()
3284 …mmy_vars.dml32_ModeSupportAndSystemConfigurationFull.myPipe.DCCEnable = mode_lib->vba.DCCEnable[k]; in dml32_ModeSupportAndSystemConfigurationFull()
[all …]
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| /drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| A D | display_mode_vba_30.c | 183 bool DCCEnable,
227 bool DCCEnable,
260 bool DCCEnable,
318 bool DCCEnable[],
1657 bool DCCEnable, in CalculateVMAndRowBytes() argument
2435 myPipe.DCCEnable = v->DCCEnable[k]; in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2754 v->DCCEnable, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2857 v->DCCEnable, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2906 v->DCCEnable, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
3029 v->DCCEnable, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
[all …]
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| /drivers/gpu/drm/amd/display/dc/dml/dcn21/ |
| A D | display_mode_vba_21.c | 104 bool DCCEnable,
172 bool DCCEnable,
235 bool DCCEnable,
267 bool DCCEnable,
311 bool DCCEnable[],
657 bool DCCEnable, in CalculatePrefetchSchedule() argument
1257 bool DCCEnable, in CalculateVMAndRowBytes() argument
3126 bool DCCEnable, in CalculateActiveRowBandwidth() argument
3180 bool DCCEnable, in CalculateFlipSchedule() argument
5265 bool DCCEnable[], in CalculateWatermarksAndDRAMSpeedChangeSupport()
[all …]
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| /drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| A D | display_mode_vba_31.c | 200 bool DCCEnable,
240 bool DCCEnable,
410 bool DCCEnable[],
459 bool DCCEnable[],
518 bool DCCEnable[],
1791 bool DCCEnable, argument
2612 myPipe.DCCEnable = v->DCCEnable[k];
3018 v->DCCEnable,
3067 v->DCCEnable,
3250 v->DCCEnable,
[all …]
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| /drivers/gpu/drm/amd/display/dc/dml/dcn314/ |
| A D | display_mode_vba_314.c | 209 bool DCCEnable,
249 bool DCCEnable,
419 bool DCCEnable[],
468 bool DCCEnable[],
527 bool DCCEnable[],
1808 bool DCCEnable, argument
2631 myPipe.DCCEnable = v->DCCEnable[k];
3037 v->DCCEnable,
3086 v->DCCEnable,
3269 v->DCCEnable,
[all …]
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| /drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| A D | display_mode_vba_20.c | 83 bool DCCEnable,
134 bool DCCEnable,
183 bool DCCEnable,
212 bool DCCEnable,
466 bool DCCEnable, in CalculatePrefetchSchedule()
589 } else if (DCCEnable) in CalculatePrefetchSchedule()
710 || DCCEnable) ? in CalculatePrefetchSchedule()
858 bool DCCEnable, in CalculateVMAndRowBytes() argument
895 if (DCCEnable == true) { in CalculateVMAndRowBytes()
3039 bool DCCEnable, in CalculateActiveRowBandwidth() argument
[all …]
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| A D | display_mode_vba_20v2.c | 108 bool DCCEnable,
158 bool DCCEnable,
207 bool DCCEnable,
236 bool DCCEnable,
558 bool DCCEnable, in CalculatePrefetchSchedule() argument
649 } else if (DCCEnable) in CalculatePrefetchSchedule()
770 || DCCEnable) ? in CalculatePrefetchSchedule()
918 bool DCCEnable, in CalculateVMAndRowBytes() argument
955 if (DCCEnable == true) { in CalculateVMAndRowBytes()
3112 bool DCCEnable, in CalculateActiveRowBandwidth() argument
[all …]
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| /drivers/gpu/drm/amd/display/dc/dml2/ |
| A D | display_mode_core.c | 235 dml_bool_t DCCEnable,
296 dml_bool_t DCCEnable,
329 dml_bool_t DCCEnable,
505 dml_bool_t DCCEnable[],
556 dml_bool_t DCCEnable[],
670 dml_bool_t DCCEnable[],
1911 dml_bool_t DCCEnable, in CalculateRowBandwidth() argument
1967 dml_bool_t DCCEnable, in CalculateFlipSchedule() argument
2451 dml_bool_t DCCEnable, in CalculateVMAndRowBytes() argument
6381 myPipe->DCCEnable = mode_lib->ms.cache_display_cfg.surface.DCCEnable[k]; in dml_prefetch_check()
[all …]
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| A D | dml2_utils.c | 106 dml_surface_array->DCCEnable[dst_index] = dml_surface_array->DCCEnable[src_index]; in dml2_util_copy_dml_surface()
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| A D | display_mode_core_structs.h | 470 dml_bool_t DCCEnable; member
592 dml_bool_t DCCEnable[__DML_NUM_PLANES__]; member
1569 dml_bool_t *DCCEnable; member
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| A D | dml2_translation_helper.c | 900 out->DCCEnable[location] = false; in populate_dummy_dml_surface_cfg()
919 out->DCCEnable[location] = in->dcc.enable; in populate_dml_surface_cfg_from_plane_state()
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| A D | display_mode_util.c | 600 dml_print("DML: surface_cfg: plane=%d, DCCEnable = %d\n", i, surface->DCCEnable[i]); in dml_print_dml_display_cfg_surface()
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| /drivers/gpu/drm/amd/display/dc/dml/ |
| A D | display_mode_structs.h | 117 bool DCCEnable; member
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| A D | display_mode_vba.h | 478 bool DCCEnable[DC__NUM_DPP__MAX]; member
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| A D | display_mode_vba.c | 609 mode_lib->vba.DCCEnable[mode_lib->vba.NumberOfActivePlanes] = in fetch_pipe_params()
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| /drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/ |
| A D | dml2_core_shared_types.h | 123 bool DCCEnable; member
1442 bool DCCEnable; member
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| A D | dml2_core_dcn4_calcs.c | 1630 if (!p->DCCEnable || !p->mrq_present) { in CalculateVMAndRowBytes()
1674 DML_LOG_VERBOSE("DML::%s: DCCEnable = %u\n", __func__, p->DCCEnable); in CalculateVMAndRowBytes()
1896 bool DCCEnable, in CalculateRowBandwidth() argument
1913 if (!DCCEnable || !mrq_present) { in CalculateRowBandwidth()
2880 scratch->calculate_vm_and_row_bytes_params.DCCEnable = p->myPipe[k].DCCEnable; in CalculateVMRowAndSwath()
2958 scratch->calculate_vm_and_row_bytes_params.DCCEnable = p->myPipe[k].DCCEnable; in CalculateVMRowAndSwath()
3136 p->myPipe[k].DCCEnable, in CalculateVMRowAndSwath()
5145 DML_LOG_VERBOSE("DML::%s: DCCEnable = %u\n", __func__, p->myPipe->DCCEnable); in CalculatePrefetchSchedule()
7426 myPipe->DCCEnable = display_cfg->plane_descriptors[k].surface.dcc.enable; in dml_core_ms_prefetch_check()
11194 myPipe->DCCEnable = display_cfg->plane_descriptors[k].surface.dcc.enable; in dml_core_mode_programming()
[all …]
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