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Searched refs:DCCG_SRII (Results 1 – 25 of 26) sorted by relevance

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/drivers/gpu/drm/amd/display/dc/dccg/dcn31/
A Ddcn31_dccg.h33 DCCG_SRII(DTO_PARAM, DPPCLK, 0),\
34 DCCG_SRII(DTO_PARAM, DPPCLK, 1),\
35 DCCG_SRII(DTO_PARAM, DPPCLK, 2),\
36 DCCG_SRII(DTO_PARAM, DPPCLK, 3),\
51 DCCG_SRII(MODULO, DTBCLK_DTO, 0),\
52 DCCG_SRII(MODULO, DTBCLK_DTO, 1),\
53 DCCG_SRII(MODULO, DTBCLK_DTO, 2),\
55 DCCG_SRII(PHASE, DTBCLK_DTO, 0),\
56 DCCG_SRII(PHASE, DTBCLK_DTO, 1),\
57 DCCG_SRII(PHASE, DTBCLK_DTO, 2),\
[all …]
/drivers/gpu/drm/amd/display/dc/dccg/dcn314/
A Ddcn314_dccg.h38 DCCG_SRII(DTO_PARAM, DPPCLK, 0),\
39 DCCG_SRII(DTO_PARAM, DPPCLK, 1),\
40 DCCG_SRII(DTO_PARAM, DPPCLK, 2),\
41 DCCG_SRII(DTO_PARAM, DPPCLK, 3),\
56 DCCG_SRII(MODULO, DTBCLK_DTO, 0),\
57 DCCG_SRII(MODULO, DTBCLK_DTO, 1),\
58 DCCG_SRII(MODULO, DTBCLK_DTO, 2),\
60 DCCG_SRII(PHASE, DTBCLK_DTO, 0),\
61 DCCG_SRII(PHASE, DTBCLK_DTO, 1),\
62 DCCG_SRII(PHASE, DTBCLK_DTO, 2),\
[all …]
/drivers/gpu/drm/amd/display/dc/dccg/dcn30/
A Ddcn30_dccg.h34 DCCG_SRII(CLOCK_CNTL, HDMICHARCLK, 0),\
35 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 2),\
36 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 3),\
37 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 4),\
38 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 5),\
/drivers/gpu/drm/amd/display/dc/dccg/dcn301/
A Ddcn301_dccg.h33 DCCG_SRII(DTO_PARAM, DPPCLK, 0),\
34 DCCG_SRII(DTO_PARAM, DPPCLK, 1),\
35 DCCG_SRII(DTO_PARAM, DPPCLK, 2),\
36 DCCG_SRII(DTO_PARAM, DPPCLK, 3),\
/drivers/gpu/drm/amd/display/dc/dccg/dcn303/
A Ddcn303_dccg.h34 DCCG_SRII(DTO_PARAM, DPPCLK, 0),\
35 DCCG_SRII(DTO_PARAM, DPPCLK, 1),\
38 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 0),\
39 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 1)
/drivers/gpu/drm/amd/display/dc/dccg/dcn20/
A Ddcn20_dccg.h33 DCCG_SRII(DTO_PARAM, DPPCLK, 0),\
34 DCCG_SRII(DTO_PARAM, DPPCLK, 1),\
35 DCCG_SRII(DTO_PARAM, DPPCLK, 2),\
36 DCCG_SRII(DTO_PARAM, DPPCLK, 3),\
38 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 0),\
39 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 1),\
44 DCCG_SRII(DTO_PARAM, DPPCLK, 4),\
45 DCCG_SRII(DTO_PARAM, DPPCLK, 5),\
46 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 2),\
47 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 3),\
[all …]
/drivers/gpu/drm/amd/display/dc/resource/dcn401/
A Ddcn401_resource.h622 SR(DPPCLK_DTO_CTRL), DCCG_SRII(DTO_PARAM, DPPCLK, 0), \
623 DCCG_SRII(DTO_PARAM, DPPCLK, 1), DCCG_SRII(DTO_PARAM, DPPCLK, 2), \
624 DCCG_SRII(DTO_PARAM, DPPCLK, 3), DCCG_SRII(CLOCK_CNTL, HDMICHARCLK, 0), \
629 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 0), DCCG_SRII(PIXEL_RATE_CNTL, OTG, 1), \
630 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 2), DCCG_SRII(PIXEL_RATE_CNTL, OTG, 3), \
634 DCCG_SRII(MODULO, DP_DTO, 0), DCCG_SRII(MODULO, DP_DTO, 1), \
635 DCCG_SRII(MODULO, DP_DTO, 2), DCCG_SRII(MODULO, DP_DTO, 3), \
636 DCCG_SRII(PHASE, DP_DTO, 0), DCCG_SRII(PHASE, DP_DTO, 1), \
637 DCCG_SRII(PHASE, DP_DTO, 2), DCCG_SRII(PHASE, DP_DTO, 3), \
A Ddcn401_resource.c159 #define DCCG_SRII(reg_name, block, id)\ macro
/drivers/gpu/drm/amd/display/dc/resource/dcn32/
A Ddcn32_resource.h1237 SR(DPPCLK_DTO_CTRL), DCCG_SRII(DTO_PARAM, DPPCLK, 0), \
1238 DCCG_SRII(DTO_PARAM, DPPCLK, 1), DCCG_SRII(DTO_PARAM, DPPCLK, 2), \
1239 DCCG_SRII(DTO_PARAM, DPPCLK, 3), DCCG_SRII(CLOCK_CNTL, HDMICHARCLK, 0), \
1244 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 0), DCCG_SRII(PIXEL_RATE_CNTL, OTG, 1), \
1245 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 2), DCCG_SRII(PIXEL_RATE_CNTL, OTG, 3), \
1246 DCCG_SRII(MODULO, DTBCLK_DTO, 0), DCCG_SRII(MODULO, DTBCLK_DTO, 1), \
1247 DCCG_SRII(MODULO, DTBCLK_DTO, 2), DCCG_SRII(MODULO, DTBCLK_DTO, 3), \
1248 DCCG_SRII(PHASE, DTBCLK_DTO, 0), DCCG_SRII(PHASE, DTBCLK_DTO, 1), \
1249 DCCG_SRII(PHASE, DTBCLK_DTO, 2), DCCG_SRII(PHASE, DTBCLK_DTO, 3), \
/drivers/gpu/drm/amd/display/dc/dccg/dcn302/
A Ddcn302_dccg.h34 DCCG_SRII(DTO_PARAM, DPPCLK, 4)
/drivers/gpu/drm/amd/display/dc/resource/dcn201/
A Ddcn201_resource.c270 #define DCCG_SRII(reg_name, block, id)\ macro
/drivers/gpu/drm/amd/display/dc/resource/dcn302/
A Ddcn302_resource.c191 #define DCCG_SRII(reg_name, block, id)\ macro
/drivers/gpu/drm/amd/display/dc/resource/dcn303/
A Ddcn303_resource.c188 #define DCCG_SRII(reg_name, block, id)\ macro
/drivers/gpu/drm/amd/display/dc/resource/dcn21/
A Ddcn21_resource.c117 #define DCCG_SRII(reg_name, block, id)\ macro
/drivers/gpu/drm/amd/display/dc/resource/dcn301/
A Ddcn301_resource.c152 #define DCCG_SRII(reg_name, block, id)\ macro
/drivers/gpu/drm/amd/display/dc/resource/dcn316/
A Ddcn316_resource.c179 #define DCCG_SRII(reg_name, block, id)\ macro
/drivers/gpu/drm/amd/display/dc/resource/dcn314/
A Ddcn314_resource.c176 #define DCCG_SRII(reg_name, block, id)\ macro
/drivers/gpu/drm/amd/display/dc/resource/dcn31/
A Ddcn31_resource.c159 #define DCCG_SRII(reg_name, block, id)\ macro
/drivers/gpu/drm/amd/display/dc/resource/dcn321/
A Ddcn321_resource.c172 #define DCCG_SRII(reg_name, block, id)\ macro
/drivers/gpu/drm/amd/display/dc/resource/dcn35/
A Ddcn35_resource.c191 #define DCCG_SRII(reg_name, block, id)\ macro
/drivers/gpu/drm/amd/display/dc/resource/dcn315/
A Ddcn315_resource.c193 #define DCCG_SRII(reg_name, block, id)\ macro
/drivers/gpu/drm/amd/display/dc/resource/dcn351/
A Ddcn351_resource.c171 #define DCCG_SRII(reg_name, block, id)\ macro
/drivers/gpu/drm/amd/display/dc/resource/dcn36/
A Ddcn36_resource.c176 #define DCCG_SRII(reg_name, block, id)\ macro
/drivers/gpu/drm/amd/display/dc/resource/dcn30/
A Ddcn30_resource.c148 #define DCCG_SRII(reg_name, block, id)\ macro
/drivers/gpu/drm/amd/display/dc/resource/dcn20/
A Ddcn20_resource.c153 #define DCCG_SRII(reg_name, block, id)\ macro

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