Home
last modified time | relevance | path

Searched refs:DCFCLKState (Results 1 – 12 of 12) sorted by relevance

/drivers/gpu/drm/amd/display/dc/dml/dcn30/
A Ddcn30_fpu.c311 double dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][maxMpcComb]; in dcn30_fpu_calculate_wm_and_dlg()
345 dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; in dcn30_fpu_calculate_wm_and_dlg()
A Ddisplay_mode_vba_30.c4628 v->DCFCLKState[i][j] = v->DCFCLKPerState[i]; in dml30_ModeSupportAndSystemConfigurationFull()
4639 if (v->DCFCLKState[i][j] < mode_lib->soc.min_dcfclk) { in dml30_ModeSupportAndSystemConfigurationFull()
4640 v->DCFCLKState[i][j] = mode_lib->soc.min_dcfclk; in dml30_ModeSupportAndSystemConfigurationFull()
4650 v->ReturnBusWidth * v->DCFCLKState[i][j], in dml30_ModeSupportAndSystemConfigurationFull()
4668 …> (v->RoundTripPingLatencyCycles + 32) / v->DCFCLKState[i][j] + ReorderingBytes / v->ReturnBWPerSt… in dml30_ModeSupportAndSystemConfigurationFull()
4727 v->DCFCLKState[i][j], in dml30_ModeSupportAndSystemConfigurationFull()
5016 v->DCFCLKState[i][j], in dml30_ModeSupportAndSystemConfigurationFull()
5170 v->DCFCLK = v->DCFCLKState[v->VoltageLevel][MaximumMPCCombine]; in dml30_ModeSupportAndSystemConfigurationFull()
6621 …v->DCFCLKState[i][j] = dml_min(v->DCFCLKPerState[i], 1.05 * (1 + mode_lib->vba.PercentMarginOverMi… in UseMinimumDCFCLK()
/drivers/gpu/drm/amd/display/dc/dml/dcn32/
A Ddisplay_mode_vba_32.c2993 mode_lib->vba.DCFCLKState[i][j] = mode_lib->vba.DCFCLKPerState[i]; in dml32_ModeSupportAndSystemConfigurationFull()
3110 mode_lib->vba.DCFCLKState); in dml32_ModeSupportAndSystemConfigurationFull()
3116 mode_lib->vba.HostVMEnable, mode_lib->vba.DCFCLKState[i][j], in dml32_ModeSupportAndSystemConfigurationFull()
3127 / mode_lib->vba.DCFCLKState[i][j] in dml32_ModeSupportAndSystemConfigurationFull()
3147 dml_min3(mode_lib->vba.ReturnBusWidth * mode_lib->vba.DCFCLKState[i][j] in dml32_ModeSupportAndSystemConfigurationFull()
3230 mode_lib->vba.DCFCLKState[i][j], mode_lib->vba.FabricClockPerState[i], in dml32_ModeSupportAndSystemConfigurationFull()
3240 mode_lib->vba.DCFCLKState[i][j], mode_lib->vba.TotalNumberOfActiveDPP[i][j], in dml32_ModeSupportAndSystemConfigurationFull()
3320 …(v->DRAMSpeedPerState[i] <= MEM_STROBE_FREQ_MHZ || v->DCFCLKState[i][j] <= DCFCLK_FREQ_EXTRA_PREFE… in dml32_ModeSupportAndSystemConfigurationFull()
3588 v->DCFCLKState[i][j], in dml32_ModeSupportAndSystemConfigurationFull()
3732 mode_lib->vba.DCFCLK = mode_lib->vba.DCFCLKState[mode_lib->vba.VoltageLevel][MaximumMPCCombine]; in dml32_ModeSupportAndSystemConfigurationFull()
A Ddisplay_mode_vba_util_32.h644 double DCFCLKState[][2]);
A Ddcn32_fpu.c479 …unsigned int dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcCo… in dcn32_set_phantom_stream_timing()
2309 …double dcfclk_from_validation = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vb… in dcn32_calculate_wm_and_dlg_fpu()
2399 …dcfclk_from_fw_based_mclk_switching = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.… in dcn32_calculate_wm_and_dlg_fpu()
A Ddisplay_mode_vba_util_32.c2978 double DCFCLKState[][2]) in dml32_UseMinimumDCFCLK()
3146 DCFCLKState[i][j] = dml_min(DCFCLKPerState[i], 1.05 * in dml32_UseMinimumDCFCLK()
/drivers/gpu/drm/amd/display/dc/dml/dcn31/
A Ddisplay_mode_vba_31.c2005 v->ReturnBusWidth * v->DCFCLKState[v->VoltageLevel][v->maxMpcComb],
5027 v->DCFCLKState[i][j] = v->DCFCLKPerState[i];
5037 v->ReturnBusWidth * v->DCFCLKState[i][j],
5059 …> (v->RoundTripPingLatencyCycles + __DML_ARB_TO_RET_DELAY__) / v->DCFCLKState[i][j] + ReorderingBy…
5078 v->ReturnBusWidth * v->DCFCLKState[i][j],
5132 v->ReturnBusWidth * v->DCFCLKState[i][j],
5143 v->DCFCLKState[i][j],
5348 v->DCFCLKState[i][j],
5534 v->DCFCLK = v->DCFCLKState[v->VoltageLevel][MaximumMPCCombine];
7181 …v->DCFCLKState[i][j] = dml_min(v->DCFCLKPerState[i], 1.05 * dml_max(DCFCLKRequiredForAverageBandwi…
A Ddcn31_fpu.c489 double dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; in dcn31_calculate_wm_and_dlg_fp()
/drivers/gpu/drm/amd/display/dc/dml/dcn314/
A Ddisplay_mode_vba_314.c2022 v->ReturnBusWidth * v->DCFCLKState[v->VoltageLevel][v->maxMpcComb],
5113 v->DCFCLKState[i][j] = v->DCFCLKPerState[i];
5123 v->ReturnBusWidth * v->DCFCLKState[i][j],
5145 …> (v->RoundTripPingLatencyCycles + __DML_ARB_TO_RET_DELAY__) / v->DCFCLKState[i][j] + ReorderingBy…
5164 v->ReturnBusWidth * v->DCFCLKState[i][j],
5218 v->ReturnBusWidth * v->DCFCLKState[i][j],
5229 v->DCFCLKState[i][j],
5434 v->DCFCLKState[i][j],
5628 v->DCFCLK = v->DCFCLKState[v->VoltageLevel][MaximumMPCCombine];
7269 …v->DCFCLKState[i][j] = dml_min(v->DCFCLKPerState[i], 1.05 * dml_max(DCFCLKRequiredForAverageBandwi…
/drivers/gpu/drm/amd/display/dc/dml2/
A Ddisplay_mode_core_structs.h828 …dml_float_t DCFCLKState[2]; /// <brief recommended DCFCLK freq; calculated by DML. If UseMinimumRe… member
1326 dml_float_t *DCFCLKState; member
A Ddisplay_mode_core.c4706 …p->DCFCLKState[j] = dml_min(p->DCFCLKPerState, 1.05 * dml_max(s->DCFCLKRequiredForAverageBandwidth… in UseMinimumDCFCLK()
6314 mode_lib->ms.DCFCLKState[j], in dml_prefetch_check()
6325 mode_lib->ms.DCFCLKState[j], in dml_prefetch_check()
6655 CalculateWatermarks_params->DCFCLK = mode_lib->ms.DCFCLKState[j]; in dml_prefetch_check()
7905 mode_lib->ms.DCFCLKState[j] = mode_lib->ms.state.dcfclk_mhz; in dml_core_mode_support()
8008 UseMinimumDCFCLK_params->DCFCLKState = mode_lib->ms.DCFCLKState; in dml_core_mode_support()
8017 …mode_lib->ms.cache_display_cfg.plane.HostVMEnable, mode_lib->ms.DCFCLKState[j], mode_lib->ms.state… in dml_core_mode_support()
8027 …(mode_lib->ms.soc.round_trip_ping_latency_dcfclk_cycles + 32) / mode_lib->ms.DCFCLKState[j] + s->R… in dml_core_mode_support()
8042 …h[j] = dml_min3(mode_lib->ms.soc.return_bus_width_bytes * mode_lib->ms.DCFCLKState[j] * mode_lib->… in dml_core_mode_support()
8240 mode_lib->ms.DCFCLK = mode_lib->ms.DCFCLKState[mode_lib->ms.support.MaximumMPCCombine]; in dml_core_mode_support()
/drivers/gpu/drm/amd/display/dc/dml/
A Ddisplay_mode_vba.h600 double DCFCLKState[DC__VOLTAGE_STATES][2]; member

Completed in 108 milliseconds