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Searched refs:DC_IP_REQUEST_CNTL (Results 1 – 23 of 23) sorted by relevance

/drivers/gpu/drm/amd/display/dc/pg/dcn35/
A Ddcn35_pg_cntl.c103 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); in pg_cntl35_dsc_pg_control()
105 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); in pg_cntl35_dsc_pg_control()
208 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); in pg_cntl35_hubp_dpp_pg_control()
210 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); in pg_cntl35_hubp_dpp_pg_control()
285 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); in pg_cntl35_hpo_pg_control()
287 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); in pg_cntl35_hpo_pg_control()
332 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); in pg_cntl35_io_clk_pg_control()
334 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); in pg_cntl35_io_clk_pg_control()
435 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); in pg_cntl35_plane_otg_pg_control()
437 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); in pg_cntl35_plane_otg_pg_control()
A Ddcn35_pg_cntl.h57 SR(DC_IP_REQUEST_CNTL)
111 PG_CNTL_SF(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh)
138 uint32_t DC_IP_REQUEST_CNTL; member
/drivers/gpu/drm/amd/display/dc/hwss/dcn302/
A Ddcn302_hwseq.c171 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); in dcn302_dsc_pg_control()
173 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); in dcn302_dsc_pg_control()
222 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); in dcn302_dsc_pg_control()
/drivers/gpu/drm/amd/display/dc/hwss/dcn31/
A Ddcn31_hwseq.c299 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); in dcn31_dsc_pg_control()
301 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); in dcn31_dsc_pg_control()
334 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); in dcn31_dsc_pg_control()
355 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); in dcn31_enable_power_gating_plane()
357 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); in dcn31_enable_power_gating_plane()
375 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); in dcn31_enable_power_gating_plane()
458 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); in dcn31_hubp_pg_control()
460 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); in dcn31_hubp_pg_control()
484 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); in dcn31_hubp_pg_control()
/drivers/gpu/drm/amd/display/dc/hwss/dcn314/
A Ddcn314_hwseq.c242 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); in dcn314_dsc_pg_control()
244 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); in dcn314_dsc_pg_control()
285 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); in dcn314_dsc_pg_control()
303 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); in dcn314_enable_power_gating_plane()
305 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); in dcn314_enable_power_gating_plane()
324 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); in dcn314_enable_power_gating_plane()
/drivers/gpu/drm/amd/display/dc/hwss/dce/
A Ddce_hwseq.h254 SR(DC_IP_REQUEST_CNTL)
319 SR(DC_IP_REQUEST_CNTL)
369 SR(DC_IP_REQUEST_CNTL)
477 SR(DC_IP_REQUEST_CNTL), \
537 SR(DC_IP_REQUEST_CNTL), \
597 uint32_t DC_IP_REQUEST_CNTL; member
831 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
896 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh)
936 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh)
988 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
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/drivers/gpu/drm/amd/display/dc/resource/dcn36/
A Ddcn36_resource.h67 SR(DC_IP_REQUEST_CNTL), \
A Ddcn36_resource.c578 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
/drivers/gpu/drm/amd/display/dc/hwss/dcn32/
A Ddcn32_hwseq.c85 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); in dcn32_dsc_pg_control()
87 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); in dcn32_dsc_pg_control()
129 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); in dcn32_dsc_pg_control()
143 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); in dcn32_enable_power_gating_plane()
145 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); in dcn32_enable_power_gating_plane()
160 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); in dcn32_enable_power_gating_plane()
/drivers/gpu/drm/amd/display/dc/hwss/dcn20/
A Ddcn20_hwseq.c317 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); in dcn20_enable_power_gating_plane()
319 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); in dcn20_enable_power_gating_plane()
353 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); in dcn20_enable_power_gating_plane()
489 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); in dcn20_dsc_pg_control()
491 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); in dcn20_dsc_pg_control()
548 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); in dcn20_dsc_pg_control()
1283 if (REG(DC_IP_REQUEST_CNTL)) { in dcn20_power_on_plane_resources()
1284 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); in dcn20_power_on_plane_resources()
1286 REG_SET(DC_IP_REQUEST_CNTL, 0, in dcn20_power_on_plane_resources()
1296 REG_SET(DC_IP_REQUEST_CNTL, 0, in dcn20_power_on_plane_resources()
/drivers/gpu/drm/amd/display/dc/hwss/dcn35/
A Ddcn35_hwseq.c516 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); in dcn35_dsc_pg_control()
518 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); in dcn35_dsc_pg_control()
559 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); in dcn35_dsc_pg_control()
571 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); in dcn35_enable_power_gating_plane()
573 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); in dcn35_enable_power_gating_plane()
/drivers/gpu/drm/amd/display/dc/hwss/dcn10/
A Ddcn10_hwseq.c981 if (REG(DC_IP_REQUEST_CNTL)) { in power_on_plane_resources()
982 REG_SET(DC_IP_REQUEST_CNTL, 0, in power_on_plane_resources()
991 REG_SET(DC_IP_REQUEST_CNTL, 0, in power_on_plane_resources()
1008 REG_SET(DC_IP_REQUEST_CNTL, 0, in undo_DEGVIDCN10_253_wa()
1012 REG_SET(DC_IP_REQUEST_CNTL, 0, in undo_DEGVIDCN10_253_wa()
1037 REG_SET(DC_IP_REQUEST_CNTL, 0, in apply_DEGVIDCN10_253_wa()
1041 REG_SET(DC_IP_REQUEST_CNTL, 0, in apply_DEGVIDCN10_253_wa()
1459 if (REG(DC_IP_REQUEST_CNTL)) { in dcn10_plane_atomic_power_down()
1460 REG_SET(DC_IP_REQUEST_CNTL, 0, in dcn10_plane_atomic_power_down()
1472 REG_SET(DC_IP_REQUEST_CNTL, 0, in dcn10_plane_atomic_power_down()
/drivers/gpu/drm/amd/display/dc/resource/dcn35/
A Ddcn35_resource.h211 SR(DC_IP_REQUEST_CNTL), \
A Ddcn35_resource.c597 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
/drivers/gpu/drm/amd/display/dc/hwss/dcn401/
A Ddcn401_hwseq.c2635 if (REG(DC_IP_REQUEST_CNTL)) { in dcn401_plane_atomic_power_down()
2636 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); in dcn401_plane_atomic_power_down()
2638 REG_SET(DC_IP_REQUEST_CNTL, 0, in dcn401_plane_atomic_power_down()
2651 if (org_ip_request_cntl == 0 && REG(DC_IP_REQUEST_CNTL)) in dcn401_plane_atomic_power_down()
2652 REG_SET(DC_IP_REQUEST_CNTL, 0, in dcn401_plane_atomic_power_down()
/drivers/gpu/drm/amd/display/dc/resource/dcn316/
A Ddcn316_resource.c724 SR(DC_IP_REQUEST_CNTL), \
758 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
/drivers/gpu/drm/amd/display/dc/resource/dcn314/
A Ddcn314_resource.c739 SR(DC_IP_REQUEST_CNTL), \
776 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
/drivers/gpu/drm/amd/display/dc/resource/dcn31/
A Ddcn31_resource.c730 SR(DC_IP_REQUEST_CNTL), \
764 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
/drivers/gpu/drm/amd/display/dc/resource/dcn321/
A Ddcn321_resource.c579 SR(DC_IP_REQUEST_CNTL), \
615 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
/drivers/gpu/drm/amd/display/dc/resource/dcn315/
A Ddcn315_resource.c729 SR(DC_IP_REQUEST_CNTL), \
763 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
/drivers/gpu/drm/amd/display/dc/resource/dcn401/
A Ddcn401_resource.c560 SR(DC_IP_REQUEST_CNTL), \
609 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
/drivers/gpu/drm/amd/display/dc/resource/dcn32/
A Ddcn32_resource.c583 SR(DC_IP_REQUEST_CNTL), \
619 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
/drivers/gpu/drm/amd/display/dc/resource/dcn351/
A Ddcn351_resource.c577 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \

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