Searched refs:DC_LOG_HW_LINK_TRAINING (Results 1 – 7 of 7) sorted by relevance
| /drivers/gpu/drm/amd/display/dc/link/protocols/ |
| A D | link_dp_training.c | 198 DC_LOG_HW_LINK_TRAINING("%s: Invalid HW Training pattern: %d\n", in dp_initialize_scrambling_data_symbols()
277 DC_LOG_HW_LINK_TRAINING("%s:\n wait = %d\n", in dp_wait_for_training_aux_rd_interval()
643 DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n" in dp_get_lane_status_and_lane_adjust()
653 DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n" in dp_get_lane_status_and_lane_adjust()
1080 DC_LOG_HW_LINK_TRAINING("%s\n %x pattern = %x\n", in dpcd_set_training_pattern()
1197 DC_LOG_HW_LINK_TRAINING("%s\n LTTPR Repeater ID: %d\n" in dpcd_set_lane_settings()
1263 DC_LOG_HW_LINK_TRAINING("%s\n 0x%X pattern = %x\n", in dpcd_set_lt_pattern_and_lane_settings()
1282 DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n" in dpcd_set_lt_pattern_and_lane_settings()
1290 DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n" in dpcd_set_lt_pattern_and_lane_settings()
1353 DC_LOG_HW_LINK_TRAINING("%s\n GPU sends TPS1. Wait 400us.\n", in start_clock_recovery_pattern_early()
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| A D | link_dp_training_dpia.c | 106 DC_LOG_HW_LINK_TRAINING("%s\n DPIA(%d) configuring\n - LTTPR mode(%d)\n", in dpia_configure_link()
255 DC_LOG_HW_LINK_TRAINING("%s\n LTTPR Repeater ID: %d\n 0x%X pattern = %x\n", in dpcd_set_lt_pattern()
261 DC_LOG_HW_LINK_TRAINING("%s\n 0x%X pattern = %x\n", in dpcd_set_lt_pattern()
405 DC_LOG_HW_LINK_TRAINING("%s: Clock recovery OK\n", __func__); in dpia_training_cr_non_transparent()
434 DC_LOG_HW_LINK_TRAINING( in dpia_training_cr_non_transparent()
509 DC_LOG_HW_LINK_TRAINING("%s: Clock recovery OK\n", __func__); in dpia_training_cr_transparent()
537 DC_LOG_HW_LINK_TRAINING("%s\n DPIA(%d) clock recovery\n -hop(%d)\n - result(%d)\n - retries(%d)\n", in dpia_training_cr_transparent()
705 DC_LOG_HW_LINK_TRAINING( in dpia_training_eq_non_transparent()
792 DC_LOG_HW_LINK_TRAINING("%s\n DPIA(%d) equalization\n - hop(%d)\n - result(%d)\n - retries(%d)\n", in dpia_training_eq_transparent()
908 DC_LOG_HW_LINK_TRAINING("%s\n DPIA(%d) end\n - hop(%d)\n - result(%d)\n - LTTPR mode(%d)\n", in dpia_training_end()
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| A D | link_dp_training_8b_10b.c | 205 DC_LOG_HW_LINK_TRAINING("%s\n GPU sends TPS2. Wait 400us.\n", __func__); in set_link_settings_and_perform_early_tps2_retimer_pre_lt_sequence()
299 DC_LOG_HW_LINK_TRAINING("%s: Clock recovery OK\n", __func__); in perform_8b_10b_clock_recovery_sequence()
463 DC_LOG_HW_LINK_TRAINING("%s: Channel EQ done.\n", __func__); in dp_perform_8b_10b_link_training()
486 DC_LOG_HW_LINK_TRAINING("%s: Channel EQ done.\n", __func__); in dp_perform_8b_10b_link_training()
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| A D | link_dp_training_128b_132b.c | 48 DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X TX_FFE_PRESET_VALUE = %x\n", in dpcd_128b_132b_set_lane_settings()
218 DC_LOG_HW_LINK_TRAINING("%s: Channel EQ done.\n", __func__); in dp_perform_128b_132b_link_training()
224 DC_LOG_HW_LINK_TRAINING("%s: CDS done.\n", __func__); in dp_perform_128b_132b_link_training()
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| A D | link_dp_training_fixed_vs_pe_retimer.c | 291 DC_LOG_HW_LINK_TRAINING("%s\n %x rate = %x\n %x lane = %x framing = %x\n %x spread = %x\n", in dp_perform_fixed_vs_pe_training_sequence()
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| A D | link_dp_capability.c | 2313 DC_LOG_HW_LINK_TRAINING("%s\n Training with LTTPR, max_lane count %d max_link rate %d \n", in dp_get_max_link_cap()
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| /drivers/gpu/drm/amd/display/include/ |
| A D | logger_types.h | 38 #define DC_LOG_HW_LINK_TRAINING(...) pr_debug("[HW_LINK_TRAINING]:"__VA_ARGS__) macro
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