Searched refs:DC_LOG_SMU (Results 1 – 17 of 17) sorted by relevance
| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/ |
| A D | dcn315_clk_mgr.c | 677 DC_LOG_SMU("NumDcfClkLevelsEnabled: %d\n" in dcn315_clk_mgr_construct()
692 DC_LOG_SMU("smu_dpm_clks.dpm_clks->DcfClocks[%d] = %d\n", in dcn315_clk_mgr_construct()
697 DC_LOG_SMU("smu_dpm_clks.dpm_clks->DispClocks[%d] = %d\n", in dcn315_clk_mgr_construct()
701 DC_LOG_SMU("smu_dpm_clks.dpm_clks->SocClocks[%d] = %d\n", in dcn315_clk_mgr_construct()
705 DC_LOG_SMU("smu_dpm_clks.dpm_clks->SocVoltage[%d] = %d\n", in dcn315_clk_mgr_construct()
709 DC_LOG_SMU("smu_dpm_clks.dpm_clks.DfPstateTable[%d].FClk = %d\n" in dcn315_clk_mgr_construct()
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| A D | dcn315_smu.c | 70 #define smu_print(str, ...) {DC_LOG_SMU(str, ##__VA_ARGS__); }
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| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/ |
| A D | dcn31_clk_mgr.c | 750 DC_LOG_SMU("NumDcfClkLevelsEnabled: %d\n" in dcn31_clk_mgr_construct()
765 DC_LOG_SMU("smu_dpm_clks.dpm_clks->DcfClocks[%d] = %d\n", in dcn31_clk_mgr_construct()
770 DC_LOG_SMU("smu_dpm_clks.dpm_clks->DispClocks[%d] = %d\n", in dcn31_clk_mgr_construct()
774 DC_LOG_SMU("smu_dpm_clks.dpm_clks->SocClocks[%d] = %d\n", in dcn31_clk_mgr_construct()
778 DC_LOG_SMU("smu_dpm_clks.dpm_clks->SocVoltage[%d] = %d\n", in dcn31_clk_mgr_construct()
782 DC_LOG_SMU("smu_dpm_clks.dpm_clks.DfPstateTable[%d].FClk = %d\n" in dcn31_clk_mgr_construct()
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| A D | dcn31_smu.c | 46 #define smu_print(str, ...) {DC_LOG_SMU(str, ##__VA_ARGS__); }
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| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/ |
| A D | dcn314_clk_mgr.c | 859 DC_LOG_SMU("NumDcfClkLevelsEnabled: %d\n" in dcn314_clk_mgr_construct()
874 DC_LOG_SMU("smu_dpm_clks.dpm_clks->DcfClocks[%d] = %d\n", in dcn314_clk_mgr_construct()
879 DC_LOG_SMU("smu_dpm_clks.dpm_clks->DispClocks[%d] = %d\n", in dcn314_clk_mgr_construct()
883 DC_LOG_SMU("smu_dpm_clks.dpm_clks->SocClocks[%d] = %d\n", in dcn314_clk_mgr_construct()
887 DC_LOG_SMU("smu_dpm_clks.dpm_clks->SocVoltage[%d] = %d\n", in dcn314_clk_mgr_construct()
891 DC_LOG_SMU("smu_dpm_clks.dpm_clks.DfPstateTable[%d].FClk = %d\n" in dcn314_clk_mgr_construct()
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| A D | dcn314_smu.c | 62 #define smu_print(str, ...) {DC_LOG_SMU(str, ##__VA_ARGS__); }
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| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/ |
| A D | dcn35_clk_mgr.c | 1345 DC_LOG_SMU("NumDcfClkLevelsEnabled: %d\n" in dcn35_clk_mgr_construct()
1362 DC_LOG_SMU("smu_dpm_clks.dpm_clks->DcfClocks[%d] = %d\n", in dcn35_clk_mgr_construct()
1367 DC_LOG_SMU("smu_dpm_clks.dpm_clks->DispClocks[%d] = %d\n", in dcn35_clk_mgr_construct()
1371 DC_LOG_SMU("smu_dpm_clks.dpm_clks->SocClocks[%d] = %d\n", in dcn35_clk_mgr_construct()
1375 DC_LOG_SMU("smu_dpm_clks.dpm_clks->FclkClocks_Freq[%d] = %d\n", in dcn35_clk_mgr_construct()
1377 DC_LOG_SMU("smu_dpm_clks.dpm_clks->FclkClocks_Voltage[%d] = %d\n", in dcn35_clk_mgr_construct()
1381 DC_LOG_SMU("smu_dpm_clks.dpm_clks->SocVoltage[%d] = %d\n", in dcn35_clk_mgr_construct()
1385 DC_LOG_SMU("smu_dpm_clks.dpm_clks.MemPstateTable[%d].UClk = %d\n" in dcn35_clk_mgr_construct()
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| A D | dcn35_smu.c | 62 #define smu_print(str, ...) {DC_LOG_SMU(str, ##__VA_ARGS__); }
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| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/ |
| A D | dcn30m_clk_mgr_smu_msg.c | 45 #define smu_print(str, ...) {DC_LOG_SMU(str, ##__VA_ARGS__); }
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| A D | dcn30_clk_mgr_smu_msg.c | 46 #define smu_print(str, ...) {DC_LOG_SMU(str, ##__VA_ARGS__); }
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| /drivers/gpu/drm/amd/display/include/ |
| A D | logger_types.h | 64 #define DC_LOG_SMU(...) pr_debug("[SMU_MSG]:"__VA_ARGS__) macro
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| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/ |
| A D | rn_clk_mgr_vbios_smu.c | 50 #define smu_print(str, ...) {DC_LOG_SMU(str, ##__VA_ARGS__); }
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| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/ |
| A D | dcn301_smu.c | 49 #define smu_print(str, ...) {DC_LOG_SMU(str, ##__VA_ARGS__); }
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| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/ |
| A D | dcn316_smu.c | 63 #define smu_print(str, ...) {DC_LOG_SMU(str, ##__VA_ARGS__); }
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| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/ |
| A D | dcn32_clk_mgr_smu_msg.c | 42 #define smu_print(str, ...) {DC_LOG_SMU(str, ##__VA_ARGS__); }
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| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/ |
| A D | dcn401_clk_mgr_smu_msg.c | 22 #define smu_print(str, ...) {DC_LOG_SMU(str, ##__VA_ARGS__); }
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| /drivers/gpu/drm/amd/display/dc/dml/dcn35/ |
| A D | dcn35_fpu.c | 614 DC_LOG_SMU("zstate_support: %d, StutterPeriod: %d\n", support, in dcn35_decide_zstate_support()
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