Searched refs:DC_SW_LINEAR (Results 1 – 12 of 12) sorted by relevance
| /drivers/gpu/drm/amd/display/dc/dce/ |
| A D | dce_mem_input.c | 636 GRPH_SW_MODE, DC_SW_LINEAR); in dce_mi_clear_tiling()
641 GRPH_ARRAY_MODE, DC_SW_LINEAR); in dce_mi_clear_tiling()
646 GRPH_ARRAY_MODE, DC_SW_LINEAR); in dce_mi_clear_tiling()
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| /drivers/gpu/drm/amd/display/dc/ |
| A D | dc_hw_types.h | 302 DC_SW_LINEAR = 0, enumerator
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| /drivers/gpu/drm/amd/display/dc/hubp/dcn30/ |
| A D | dcn30_hubp.c | 342 REG_UPDATE(DCSURF_TILING_CONFIG, SW_MODE, DC_SW_LINEAR); in hubp3_clear_tiling()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| A D | dcn32_resource_helpers.c | 404 … && !disable_unbounded_requesting && pipe->plane_state->tiling_info.gfx9.swizzle != DC_SW_LINEAR) { in dcn32_set_det_allocations()
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| /drivers/gpu/drm/amd/display/dc/dml/calcs/ |
| A D | dcn_calcs.c | 165 case DC_SW_LINEAR: in tl_sw_mode_to_bw_defs()
258 case DC_SW_LINEAR: in swizzle_mode_to_macro_tile_size()
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| /drivers/gpu/drm/amd/display/dc/hubp/dcn401/ |
| A D | dcn401_hubp.c | 528 REG_UPDATE(DCSURF_TILING_CONFIG, SW_MODE, DC_SW_LINEAR); in hubp401_clear_tiling()
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| /drivers/gpu/drm/amd/display/dc/core/ |
| A D | dc_hw_sequencer.c | 1129 case DC_SW_LINEAR: in get_surface_tile_visual_confirm_color()
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| /drivers/gpu/drm/amd/display/dc/hubp/dcn10/ |
| A D | dcn10_hubp.c | 526 REG_UPDATE(DCSURF_TILING_CONFIG, SW_MODE, DC_SW_LINEAR); in hubp1_clear_tiling()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn10/ |
| A D | dcn10_resource.c | 1216 enum swizzle_mode_values swizzle = DC_SW_LINEAR; in dcn10_patch_unknown_plane_state()
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| /drivers/gpu/drm/amd/display/dc/dml2/dml21/ |
| A D | dml21_translation_helper.c | 667 case DC_SW_LINEAR: in gfx9_to_dml2_swizzle_mode()
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| /drivers/gpu/drm/amd/display/dc/hubp/dcn20/ |
| A D | dcn20_hubp.c | 414 REG_UPDATE(DCSURF_TILING_CONFIG, SW_MODE, DC_SW_LINEAR); in hubp2_clear_tiling()
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| /drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| A D | dcn20_fpu.c | 1258 case DC_SW_LINEAR: in swizzle_to_dml_params()
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