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Searched refs:DC__NUM_DPP__MAX (Results 1 – 11 of 11) sorted by relevance

/drivers/gpu/drm/amd/display/dc/dml/
A Ddisplay_mode_vba.h452 bool DRRDisplay[DC__NUM_DPP__MAX];
465 double HRatio[DC__NUM_DPP__MAX];
466 double VRatio[DC__NUM_DPP__MAX];
478 bool DCCEnable[DC__NUM_DPP__MAX];
479 bool FECEnable[DC__NUM_DPP__MAX];
498 bool Interlace[DC__NUM_DPP__MAX];
504 double DCCRate[DC__NUM_DPP__MAX];
821 double Tno_bw[DC__NUM_DPP__MAX];
951 double DPPCLK[DC__NUM_DPP__MAX];
1013 double Tdmdl[DC__NUM_DPP__MAX];
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A Ddisplay_mode_vba.c261 ASSERT(plane_idx < DC__NUM_DPP__MAX); in get_pipe_idx()
263 for (i = 0; i < DC__NUM_DPP__MAX ; i++) { in get_pipe_idx()
520 unsigned int OTGInstPlane[DC__NUM_DPP__MAX]; in fetch_pipe_params()
522 bool PlaneVisited[DC__NUM_DPP__MAX]; in fetch_pipe_params()
523 bool visited[DC__NUM_DPP__MAX]; in fetch_pipe_params()
1114 ASSERT(total_pipes <= DC__NUM_DPP__MAX); in ModeSupportAndSystemConfiguration()
A Ddc_features.h45 #define DC__NUM_DPP__MAX 8 macro
/drivers/gpu/drm/amd/display/dc/dml/dcn32/
A Ddisplay_mode_vba_util_32.h619 double RequiredDPPCLKPerSurface[][2][DC__NUM_DPP__MAX],
622 unsigned int NoOfDPP[][2][DC__NUM_DPP__MAX],
624 double MaximumVStartup[][2][DC__NUM_DPP__MAX],
628 double PrefetchLinesY[][2][DC__NUM_DPP__MAX],
629 double PrefetchLinesC[][2][DC__NUM_DPP__MAX],
630 unsigned int swath_width_luma_ub_all_states[][2][DC__NUM_DPP__MAX],
631 unsigned int swath_width_chroma_ub_all_states[][2][DC__NUM_DPP__MAX],
636 double PDEAndMetaPTEBytesPerFrame[][2][DC__NUM_DPP__MAX],
637 double DPTEBytesPerRow[][2][DC__NUM_DPP__MAX],
638 double MetaRowBytes[][2][DC__NUM_DPP__MAX],
A Ddisplay_mode_vba_util_32.c466 double SwathWidthdoubleDPP[DC__NUM_DPP__MAX]; in dml32_CalculateSwathAndDETConfiguration()
2956 unsigned int NoOfDPP[][2][DC__NUM_DPP__MAX], in dml32_UseMinimumDCFCLK()
2962 double PrefetchLinesY[][2][DC__NUM_DPP__MAX], in dml32_UseMinimumDCFCLK()
2963 double PrefetchLinesC[][2][DC__NUM_DPP__MAX], in dml32_UseMinimumDCFCLK()
2972 double MetaRowBytes[][2][DC__NUM_DPP__MAX], in dml32_UseMinimumDCFCLK()
2999 unsigned int NoOfDPPState[DC__NUM_DPP__MAX]; in dml32_UseMinimumDCFCLK()
4305 bool SynchronizedSurfaces[DC__NUM_DPP__MAX][DC__NUM_DPP__MAX]; in dml32_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport()
4308 double LinesInDETY[DC__NUM_DPP__MAX]; in dml32_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport()
4309 double LinesInDETC[DC__NUM_DPP__MAX]; in dml32_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport()
6304 double SwathSizePerSurfaceY[DC__NUM_DPP__MAX]; in dml32_CalculateDETSwathFillLatencyHiding()
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/drivers/gpu/drm/amd/display/dc/dml/dcn30/
A Ddisplay_mode_vba_30.c3045 int BytePerPixY[DC__NUM_DPP__MAX] = { 0 }; in DisplayPipeConfiguration()
3046 int BytePerPixC[DC__NUM_DPP__MAX] = { 0 }; in DisplayPipeConfiguration()
3051 double dummy1[DC__NUM_DPP__MAX] = { 0 }; in DisplayPipeConfiguration()
3052 double dummy2[DC__NUM_DPP__MAX] = { 0 }; in DisplayPipeConfiguration()
3053 double dummy3[DC__NUM_DPP__MAX] = { 0 }; in DisplayPipeConfiguration()
3054 double dummy4[DC__NUM_DPP__MAX] = { 0 }; in DisplayPipeConfiguration()
3055 int dummy5[DC__NUM_DPP__MAX] = { 0 }; in DisplayPipeConfiguration()
3056 int dummy6[DC__NUM_DPP__MAX] = { 0 }; in DisplayPipeConfiguration()
3057 bool dummy7[DC__NUM_DPP__MAX] = { 0 }; in DisplayPipeConfiguration()
5241 double LinesInDETY[DC__NUM_DPP__MAX] = { 0 }; in CalculateWatermarksAndDRAMSpeedChangeSupport()
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/drivers/gpu/drm/amd/display/dc/dml/dcn31/
A Ddisplay_mode_vba_31.c3271 int BytePerPixY[DC__NUM_DPP__MAX];
3272 int BytePerPixC[DC__NUM_DPP__MAX];
3277 double dummy1[DC__NUM_DPP__MAX];
3278 double dummy2[DC__NUM_DPP__MAX];
3279 double dummy3[DC__NUM_DPP__MAX];
3280 double dummy4[DC__NUM_DPP__MAX];
3281 int dummy5[DC__NUM_DPP__MAX];
3282 int dummy6[DC__NUM_DPP__MAX];
3283 bool dummy7[DC__NUM_DPP__MAX];
5572 double LinesInDETY[DC__NUM_DPP__MAX];
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/drivers/gpu/drm/amd/display/dc/dml/dcn314/
A Ddisplay_mode_vba_314.c3290 int BytePerPixY[DC__NUM_DPP__MAX];
3291 int BytePerPixC[DC__NUM_DPP__MAX];
3296 double dummy1[DC__NUM_DPP__MAX];
3297 double dummy2[DC__NUM_DPP__MAX];
3298 double dummy3[DC__NUM_DPP__MAX];
3299 double dummy4[DC__NUM_DPP__MAX];
3300 int dummy5[DC__NUM_DPP__MAX];
3301 int dummy6[DC__NUM_DPP__MAX];
3302 bool dummy7[DC__NUM_DPP__MAX];
5666 double LinesInDETY[DC__NUM_DPP__MAX];
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/drivers/gpu/drm/amd/display/dc/dml/dcn21/
A Ddisplay_mode_vba_21.c5303 double LinesInDETY[DC__NUM_DPP__MAX]; in CalculateWatermarksAndDRAMSpeedChangeSupport()
5305 unsigned int LinesInDETYRoundedDownToSwath[DC__NUM_DPP__MAX]; in CalculateWatermarksAndDRAMSpeedChangeSupport()
5307 double FullDETBufferingTimeY[DC__NUM_DPP__MAX]; in CalculateWatermarksAndDRAMSpeedChangeSupport()
/drivers/gpu/drm/amd/display/dc/dml/dcn20/
A Ddisplay_mode_vba_20.c2233 double final_flip_bw[DC__NUM_DPP__MAX]; in dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2234 unsigned int ImmediateFlipBytes[DC__NUM_DPP__MAX]; in dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
A Ddisplay_mode_vba_20v2.c2267 double final_flip_bw[DC__NUM_DPP__MAX]; in dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2268 unsigned int ImmediateFlipBytes[DC__NUM_DPP__MAX]; in dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()

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