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Searched refs:DC__VOLTAGE_STATES (Results 1 – 13 of 13) sorted by relevance

/drivers/gpu/drm/amd/display/dc/dml/
A Ddisplay_mode_vba.h599 double DCFCLKPerState[DC__VOLTAGE_STATES];
600 double DCFCLKState[DC__VOLTAGE_STATES][2];
602 double SOCCLKPerState[DC__VOLTAGE_STATES];
603 double PHYCLKPerState[DC__VOLTAGE_STATES];
605 double MaxDppclk[DC__VOLTAGE_STATES];
606 double MaxDSCCLK[DC__VOLTAGE_STATES];
608 double MaxDispclk[DC__VOLTAGE_STATES];
764 bool ModeSupport[DC__VOLTAGE_STATES][2];
766 bool DIOSupport[DC__VOLTAGE_STATES];
771 bool ROBSupport[DC__VOLTAGE_STATES][2];
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A Ddc_features.h39 #define DC__VOLTAGE_STATES 40 macro
A Ddisplay_mode_structs.h182 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES];
/drivers/gpu/drm/amd/display/dc/dml/dcn302/
A Ddcn302_fpu.c200 unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0}; in dcn302_fpu_update_bw_bounding_box()
201 unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0}; in dcn302_fpu_update_bw_bounding_box()
202 unsigned int optimal_uclk_for_dcfclk_sta_targets[DC__VOLTAGE_STATES] = {0}; in dcn302_fpu_update_bw_bounding_box()
203 unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0}; in dcn302_fpu_update_bw_bounding_box()
205 unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {694, 875, 1000, 1200}; in dcn302_fpu_update_bw_bounding_box()
282 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { in dcn302_fpu_update_bw_bounding_box()
296 while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) { in dcn302_fpu_update_bw_bounding_box()
301 while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES && in dcn302_fpu_update_bw_bounding_box()
/drivers/gpu/drm/amd/display/dc/dml/dcn303/
A Ddcn303_fpu.c196 unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0}; in dcn303_fpu_update_bw_bounding_box()
197 unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0}; in dcn303_fpu_update_bw_bounding_box()
198 unsigned int optimal_uclk_for_dcfclk_sta_targets[DC__VOLTAGE_STATES] = {0}; in dcn303_fpu_update_bw_bounding_box()
199 unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0}; in dcn303_fpu_update_bw_bounding_box()
201 unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {694, 875, 1000, 1200}; in dcn303_fpu_update_bw_bounding_box()
287 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { in dcn303_fpu_update_bw_bounding_box()
302 while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) { in dcn303_fpu_update_bw_bounding_box()
307 while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES && in dcn303_fpu_update_bw_bounding_box()
/drivers/gpu/drm/amd/display/dc/dml/dcn321/
A Ddcn321_fpu.c354 unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {199, 615, 906, 1324, 1564}; in build_synthetic_soc_states()
712 unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0}; in dcn321_update_bw_bounding_box_fpu()
713 unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0}; in dcn321_update_bw_bounding_box_fpu()
714 unsigned int optimal_uclk_for_dcfclk_sta_targets[DC__VOLTAGE_STATES] = {0}; in dcn321_update_bw_bounding_box_fpu()
715 unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0}; in dcn321_update_bw_bounding_box_fpu()
717 unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {615, 906, 1324, 1564}; in dcn321_update_bw_bounding_box_fpu()
781 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { in dcn321_update_bw_bounding_box_fpu()
795 while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) { in dcn321_update_bw_bounding_box_fpu()
800 while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES && in dcn321_update_bw_bounding_box_fpu()
/drivers/gpu/drm/amd/display/dc/resource/dcn30/
A Ddcn30_resource.c2103 unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0}; in dcn30_update_bw_bounding_box()
2104 unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0}; in dcn30_update_bw_bounding_box()
2105 unsigned int optimal_uclk_for_dcfclk_sta_targets[DC__VOLTAGE_STATES] = {0}; in dcn30_update_bw_bounding_box()
2106 unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0}; in dcn30_update_bw_bounding_box()
2108 unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {694, 875, 1000, 1200}; in dcn30_update_bw_bounding_box()
2194 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { in dcn30_update_bw_bounding_box()
2208 while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) { in dcn30_update_bw_bounding_box()
2213 while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES && in dcn30_update_bw_bounding_box()
/drivers/gpu/drm/amd/display/dc/dml/dcn32/
A Ddcn32_fpu.c2812 unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {199, 615, 906, 1324, 1564}; in build_synthetic_soc_states()
3155 unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0}; in dcn32_update_bw_bounding_box_fpu()
3156 unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0}; in dcn32_update_bw_bounding_box_fpu()
3157 unsigned int optimal_uclk_for_dcfclk_sta_targets[DC__VOLTAGE_STATES] = {0}; in dcn32_update_bw_bounding_box_fpu()
3158 unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0}; in dcn32_update_bw_bounding_box_fpu()
3162 unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {199, 615, 906, 1324, 1564}; in dcn32_update_bw_bounding_box_fpu()
3231 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { in dcn32_update_bw_bounding_box_fpu()
3245 while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) { in dcn32_update_bw_bounding_box_fpu()
3250 while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES && in dcn32_update_bw_bounding_box_fpu()
A Ddisplay_mode_vba_util_32.c2984 double TotalMaxPrefetchFlipDPTERowBandwidth[DC__VOLTAGE_STATES][2]; in dml32_UseMinimumDCFCLK()
2987 for (i = 0; i < DC__VOLTAGE_STATES; ++i) { in dml32_UseMinimumDCFCLK()
/drivers/gpu/drm/amd/display/dc/
A Ddc.h1724 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES];
/drivers/gpu/drm/amd/display/dc/dml/dcn30/
A Ddisplay_mode_vba_30.c6496 double TotalMaxPrefetchFlipDPTERowBandwidth[DC__VOLTAGE_STATES][2] = { { 0 } }; in UseMinimumDCFCLK()
/drivers/gpu/drm/amd/display/dc/dml/dcn31/
A Ddisplay_mode_vba_31.c7033 double TotalMaxPrefetchFlipDPTERowBandwidth[DC__VOLTAGE_STATES][2];
/drivers/gpu/drm/amd/display/dc/dml/dcn314/
A Ddisplay_mode_vba_314.c7120 double TotalMaxPrefetchFlipDPTERowBandwidth[DC__VOLTAGE_STATES][2];

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