Searched refs:DDC_DDCMCTL1 (Results 1 – 1 of 1) sorted by relevance
| /drivers/gpu/drm/mediatek/ |
| A D | mtk_hdmi_ddc.c | 34 #define DDC_DDCMCTL1 (0x4) macro
105 sif_write_mask(ddc, DDC_DDCMCTL1, DDCM_SIF_MODE_MASK, in ddcm_trigger_mode()
107 sif_set_bit(ddc, DDC_DDCMCTL1, DDCM_TRI); in ddcm_trigger_mode()
108 readl_poll_timeout(ddc->regs + DDC_DDCMCTL1, val, in ddcm_trigger_mode()
122 sif_write_mask(ddc, DDC_DDCMCTL1, DDCM_PGLEN_MASK, DDCM_PGLEN_OFFSET, in mtk_hdmi_ddc_read_msg()
125 ack = sif_read_mask(ddc, DDC_DDCMCTL1, DDCM_ACK_MASK, DDCM_ACK_OFFSET); in mtk_hdmi_ddc_read_msg()
146 sif_write_mask(ddc, DDC_DDCMCTL1, DDCM_PGLEN_MASK, in mtk_hdmi_ddc_read_msg()
152 ack = sif_read_mask(ddc, DDC_DDCMCTL1, DDCM_ACK_MASK, in mtk_hdmi_ddc_read_msg()
195 sif_write_mask(ddc, DDC_DDCMCTL1, DDCM_PGLEN_MASK, DDCM_PGLEN_OFFSET, in mtk_hdmi_ddc_write_msg()
199 ack = sif_read_mask(ddc, DDC_DDCMCTL1, DDCM_ACK_MASK, DDCM_ACK_OFFSET); in mtk_hdmi_ddc_write_msg()
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