Searched refs:DDC_DDCMD0 (Results 1 – 1 of 1) sorted by relevance
| /drivers/gpu/drm/mediatek/ |
| A D | mtk_hdmi_ddc.c | 47 #define DDC_DDCMD0 (0x8) macro
121 sif_write_mask(ddc, DDC_DDCMD0, 0xff, 0, (msg->addr << 1) | 0x01); in mtk_hdmi_ddc_read_msg()
171 offset = DDC_DDCMD0; in mtk_hdmi_ddc_read_msg()
193 sif_write_mask(ddc, DDC_DDCMD0, DDCM_DATA0, 0, msg->addr << 1); in mtk_hdmi_ddc_write_msg()
194 sif_write_mask(ddc, DDC_DDCMD0, DDCM_DATA1, 8, msg->buf[0]); in mtk_hdmi_ddc_write_msg()
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